QC-LDPC Parity Check Matrix for 3888-Bit 2/3 Code Rate
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Solution Overview
Problem
Existing communication systems using LDPC codes face limitations in block length and code rate, particularly with the longest block length supported in 802.11 standards being 1944 bits and a code rate of 1/2, which restricts achievable gains in radio channels.
Innovation Solution
The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a code rate of 2/3 and a block size of 3888 bits, utilizing a binary parity check matrix and an exponent matrix to enhance encoding and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length is increased beyond 1944 bits, then the achievable gains in radio channels are improved, but the complexity of the LDPC code structure increases
Solution Approach 1:
The parity check matrix H is divided into multiple submatrices (H1, H2, H3, H4, H5, H6) arranged in a block structure. Each submatrix corresponds to specific functional groups (information bits, first parity bits, second parity bits), enabling independent processing and reducing overall computational complexity while supporting extended block lengths.
Solution Approach 2:
The patent employs a dynamic code rate adjustment mechanism where different code rates (1/2, 2/3, 3/4) are achieved by selectively including or excluding certain submatrices in the parity check matrix. This allows the system to adapt between different reliability and complexity requirements without redesigning the entire code structure.
2Productivity
If the code rate is increased from 1/2 to 2/3, then the data transmission efficiency is improved, but the error correction capability deteriorates
Solution Approach 1:
The patent changes the structural parameters of the parity check matrix to achieve different code rates. For code rate 1/2, all submatrices (H1-H6) are included; for code rate 2/3, certain submatrices are excluded or modified. This parameter adjustment maintains error correction capability while improving transmission efficiency at higher code rates.
Solution Approach 2:
The unified parity check matrix structure serves multiple functions across different code rates. The same base matrix framework supports both code rate 1/2 (higher error correction) and code rate 2/3 (higher efficiency) by selectively activating different submatrix combinations, making the system universally applicable to various channel conditions.
3Reliability
If a complex encoding process is used to generate parity bits, then the error correction capability is improved, but the encoding complexity increases
Solution Approach 1:
The encoding process is segmented into distinct stages corresponding to different submatrices (H1-H6). Each submatrix processes specific bit groups independently, allowing parallel computation and reducing overall encoding complexity while maintaining strong error correction through the cumulative effect of all submatrices.
Solution Approach 2:
The patent implements partial matrix multiplication where only necessary submatrices are applied based on the desired code rate. For code rate 2/3, fewer submatrix operations are performed compared to code rate 1/2, reducing encoding complexity while still providing sufficient error correction capability for the application.
Data Source
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AI summary
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 2/3 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 192 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.