QC-LDPC 3/4 Code Layout for 3888-Bit Block Encoding
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Solution Overview
Problem
Existing communication systems using LDPC codes face limitations in block length and code rate, particularly with the longest code supported in 802.11n-802.11be standards having a block length of 1944 bits, which restricts achievable gains in radio channels.
Innovation Solution
The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 3/4, which allows for efficient encoding and decoding processes by utilizing a binary parity check matrix and an exponent matrix with specific values and permutations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC codes is increased beyond 1944 bits, then error correction capability and coding gain are improved, but system complexity and implementation difficulty increase
Solution Approach 1:
The patent segments the large block length LDPC code into multiple smaller code blocks that can be processed independently or in parallel. This segmentation reduces the complexity of encoding and decoding operations while maintaining the overall error correction capability through concatenation or interleaving of the smaller blocks.
Solution Approach 2:
The patent introduces a new dimensional structure by organizing the LDPC code in a multi-dimensional array format rather than a simple linear sequence. This allows for more efficient memory access patterns, parallel processing, and reduced computational complexity while achieving the desired block length and error correction performance.
2Reliability
If the code rate is adjusted to optimize performance for specific channel conditions, then communication reliability is improved, but adaptability to different channel conditions decreases
Solution Approach 1:
The patent implements dynamic code rate adjustment mechanisms that allow the LDPC encoder to adaptively select optimal code rates based on current channel conditions. This is achieved through feedback loops and channel quality estimation, enabling the system to switch between different code rates (e.g., 1/2, 2/3, 3/4) to maximize reliability under varying conditions.
Solution Approach 2:
The patent changes key parameters of the LDPC code including block length, code rate, and parity check matrix structure to optimize performance for different channel conditions. By having multiple pre-configured code variants with different parameters, the system can select the most appropriate configuration based on real-time channel quality measurements.
Data Source
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AI summary
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.