QC-LDPC Parity Matrix Layout for 3888-Bit 802.11 Code Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current communication systems using LDPC codes are limited by the longest block length supported in 802.11 standards, which restricts the gain in radio channels, particularly in 2x2 multiple-input and multiple-output channels.
Innovation Solution
The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 and a code rate of 1/2, which is twice the longest block length supported in 802.11n-802.11be standards, using a parity check matrix with a cyclic structure that repeats in a quasi-cyclic manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond 1944 bits to improve channel gain, then the coding performance and error correction capability are improved, but the compatibility with existing 802.11 standards is reduced and implementation complexity increases
Solution Approach 1:
The patent segments the 3888-bit block into two separate 1944-bit blocks, each processed by standard LDPC encoding/decoding units. This segmentation allows existing hardware to handle longer blocks through multiple passes while maintaining compatibility with standard block lengths, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The patent employs a nested structure where two 1944-bit LDPC code blocks are nested within a single 3888-bit transmission frame. The outer code operates at the frame level while inner codes operate at the block level, creating a hierarchical coding scheme that achieves enhanced error correction capability while reusing existing 1944-bit code structures
2Reliability
If a new LDPC code with block length 3888 is implemented to improve MIMO channel performance, then the gain in 2x2 MIMO channels is improved, but the compatibility with existing modulation schemes and code rates is reduced
Solution Approach 1:
The patent designs the 3888-bit LDPC code structure to be universally compatible with existing 802.11 modulation schemes (BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM) and code rates (1/2, 2/3, 3/4). The code structure acts as a universal foundation that can be adapted to different modulation and coding rate requirements without requiring separate code designs, thereby improving MIMO performance while maintaining broad adaptability
3Reliability
If the code block length is doubled from 1944 to 3888 bits to increase coding gain, then the error correction performance is improved, but the processing time and computational complexity are increased
Solution Approach 1:
By segmenting the 3888-bit block into two 1944-bit blocks, the patent enables parallel or sequential processing using existing fast decoders designed for 1944-bit blocks. This segmentation reduces the processing time compared to implementing a completely new 3888-bit decoder, as the computational burden is distributed across multiple smaller, optimized processing units
Solution Approach 2:
The patent performs preliminary segmentation and organization of the 3888-bit block into two 1944-bit sub-blocks before decoding. This preliminary structuring allows the system to prepare processing buffers, initialize decoders, and organize computational resources in advance, reducing the actual decoding time when using existing hardware optimized for standard block lengths
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An apparatus may include a transmitter (120) and one or more processors (2010). The one or more processors (2010) may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check, QC-LDPC, code according to a code rate of 1/2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors (2010) may encode data using the second parity check matrix. The transmitter (120) may be configured to transmit the encoded data.