QC-LDPC 5/6 Code Structure for 3888-Bit MIMO Gain

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing communication systems using LDPC codes are limited by short block lengths, such as 1944 bits, which restricts the gain in radio channels, especially in 2×2 MIMO channels.

Innovation Solution

The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 5/6, which supports longer block lengths and enhances encoding and decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a short block length of 1944 bits is used in LDPC codes, then the device complexity and processing time are reduced, but the gain in radio channels especially in 2×2 MIMO channels is limited

Engineering Contradiction:
Improvegain in radio channelsVSAvoidblock length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent changes the block length parameter from 1944 bits to 3888 bits in the LDPC code structure. This parameter change enables achieving approximately 2 dB gain in 2×2 MIMO channels while maintaining the quasi-cyclic structure for efficient encoding and decoding. The extended block length provides better error correction performance without proportionally increasing complexity due to the QC-LDPC structure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a block length of 3888 bits is used in QC-LDPC codes, then the gain in 2×2 MIMO channels and error correction capabilities are improved, but the encoding and decoding process becomes more complex

Engineering Contradiction:
Improveerror correction capabilitiesVSAvoidencoding and decoding process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a quasi-cyclic structure that segments the large 3888-bit block into smaller cyclic sub-blocks of 162 bits. This segmentation allows the encoding and decoding processes to be performed on manageable sub-blocks rather than the entire large block, significantly reducing the computational complexity and memory requirements while maintaining the benefits of the extended block length for improved error correction capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent specifies precise parameters including block length of 3888 bits, sub-block length of 162 bits, and code rate of 5/6. These parameter changes are optimized to achieve the best balance between error correction performance and computational complexity, enabling practical implementation of QC-LDPC codes with extended block lengths.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If existing LDPC codes with limited block lengths are used, then the implementation is simpler and more widely compatible, but the communication reliability in noisy channels is insufficient

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidcompatibility with existing systems
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent designs the QC-LDPC code with a universal structure that can operate at multiple code rates (5/6, 4/5, 3/4, 2/3, 1/2) by puncturing or shortening the base code. This multi-functionality allows the same underlying code structure to be adapted to different communication requirements and channel conditions, improving compatibility with existing systems while providing enhanced reliability through the extended 3888-bit block length.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250047305A1System and method for low density parity check (LDPC) code with 5/6 code rate
Publication Date: 2025.02.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20250047305A1 patent drawing
  • US20250047305A1 patent drawing
  • US20250047305A1 patent drawing

AI summary

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.