QC-LDPC Parity Check Matrix for 7776-Bit 3/4 Code Blocks

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a block length of 1944 bits, which restricts the gain in radio channels, and LDPC codes with high-density generator matrices are computationally intensive, making them impractical for efficient encoding and decoding.

Innovation Solution

Implementing a quasi-cyclic low-density parity-check (QC-LDPC) code with a block length of 7776 bits and a code rate of 3/4, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to generate efficient encoding and decoding processes, allowing for parallel decoding and re-use of existing circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a block length of 1944 bits is used in existing wireless communication standards, then the system maintains compatibility with current standards, but the gain in radio channels is restricted

Engineering Contradiction:

Improvechannel performanceVSAvoidblock length flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the block length parameter from the standard 1944 bits to 7776 bits (a fourfold increase), and adjusts the code rate to 3/4. This parameter change enables better channel performance and radio frequency gain while maintaining the QC-LDPC code structure, directly resolving the contradiction between reliability and adaptability

Inventive Principle:

Principle #35Parameter changes

2Reliability

If LDPC codes with high-density generator matrices are used, then encoding and decoding can be performed, but the computational complexity becomes intensive and impractical

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by using a quasi-cyclic structure where the parity check matrix consists of cyclic submatrices with specific local patterns. This structure allows efficient encoding and decoding algorithms to be applied locally, reducing overall computational complexity while maintaining error correction capability

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes from high-density generator matrices to a quasi-cyclic parity check matrix structure with code rate 3/4 and block length 7776. This structural parameter change enables more efficient implementation with reduced computational complexity while maintaining or improving error correction performance

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260012204A1Systems and methods for quasi-cyclic low density parity check (QC-LDPC) code with 3/4 code rate

Publication Date: 2026.01.08 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate R of 3/4, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. The one or more processors may be configured to encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data. In some implementations, the code block size of the second QC-LDPC code may be 7776 bits.