QC-LDPC Parity Check Matrix for 7776-Bit 1/2-Rate Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a block length of 1944 bits, which restricts the gain in radio channels, particularly in 2x2 multiple-input and multiple-output channels, and require computationally intensive encoding due to high-density generator matrices.
Innovation Solution
Implementing a quasi-cyclic low-density parity-check (QC-LDPC) code with a block length of 7776 bits and a code rate of 1/2, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to simplify encoding and decoding processes, allowing for efficient encoding and decoding of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block length of 1944 bits is used in existing wireless communication standards, then the encoding process can be completed with current circuitry, but the gain in radio channels is restricted and the code rate is limited
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices with a quasi-cyclic structure, where each sub-matrix can be processed independently. This segmentation allows the encoding process to be broken down into smaller, more manageable operations that can be performed in parallel, reducing overall encoding complexity while supporting longer block lengths of 7776 bits
Solution Approach 2:
The patent changes the code rate parameter from traditional values to 1/2, and increases the block length parameter to 7776 bits. These parameter changes are achieved through a systematic construction method using Khatri-Rao lifting that maintains matrix properties while enabling longer blocks and simpler encoding operations
2Reliability
If high-density generator matrices are used for encoding, then complete error correction capability is achieved, but the encoding process becomes computationally intensive
Solution Approach 1:
Instead of using a high-density generator matrix for encoding, the patent inverts the approach by using a low-density parity check matrix for decoding. This inversion allows the system to achieve the same error correction capability while significantly reducing the computational complexity of the encoding operation, as the quasi-cyclic structure enables efficient parity check computations
Solution Approach 2:
The patent replaces the traditional mechanical matrix multiplication encoding process with a quasi-cyclic LDPC encoding approach that uses a structured parity check matrix. This substitution transforms the encoding operation from a computationally intensive full matrix operation to a simplified process that exploits the repetitive quasi-cyclic pattern, reducing computational power requirements
3Reliability
If longer block lengths are implemented to increase gain in radio channels, then communication reliability improves, but the encoding and decoding processes become more complex
Solution Approach 1:
The quasi-cyclic structure of the parity check matrix contains nested patterns where smaller cyclic sub-matrices are arranged in a larger cyclic framework. This nested structure allows the encoding and decoding processes for long block lengths to reuse the same basic computational building blocks multiple times, reducing overall complexity while achieving 7776-bit block lengths
Solution Approach 2:
The quasi-cyclic parity check matrix structure serves multiple functions simultaneously: it enables longer block lengths, provides error correction capability, and facilitates parallel processing. The same structural pattern is used throughout the matrix, allowing a single decoding algorithm to handle the entire 7776-bit block without requiring different processing for different segments, thus reducing device complexity
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Transmitter or receiver configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check, QC-LDPC, code according to a code rate R of 1/2, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. Encode or decode code data using the second parity check matrix. The code block size of the second QC-LDPC code may be 7776 bits.