QC-LDPC Block-Kronecker Coding for Longer 3/4 Rate Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wireless communication systems face limitations in achieving significant gains in error correction due to the limited block length and complexity of LDPC codes, particularly in 802.11 standards, which hinder efficient encoding and decoding processes.
Innovation Solution
The implementation of a quasi-cyclic low-density parity-check (QC-LDPC) code with a block length of 3888 and a code rate of 3/4, utilizing a Khatri-Rao lifting scheme to generate parity check matrices, which simplifies encoding and decoding processes by employing a binary matrix and exponent matrices to achieve efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond 1944 bits to improve error correction performance and gain in radio channels, then the coding gain and reliability are improved, but the complexity of encoding and decoding processes increases and computational resources are strained
Solution Approach 1:
The patent divides the LDPC code into two distinct types: first type LDPC code with block length 1944 bits and second type LDPC code with block length 3888 bits. This segmentation allows the system to handle different block lengths using specialized structures, where the larger 3888-bit code benefits from the quasi-cyclic structure that reduces complexity compared to a generic implementation, thus resolving the contradiction between increased reliability and reduced complexity.
Solution Approach 2:
The patent changes the block length parameter from 1944 bits to 3888 bits while maintaining the code rate of 3/4. This parameter change enables longer block processing which improves error correction performance and coding gain in radio channels, particularly in 2x2 MIMO channels, while the quasi-cyclic structure ensures the complexity increase is manageable.
2Reliability
If the block length is doubled from 1944 to 3888 bits to achieve consistent gains across all modulation schemes, then the coding gain increases by about 2 dB, but the processing time and computational load increase
Solution Approach 1:
The patent segments the code into two types with different block lengths, allowing the system to select appropriate code types based on channel conditions and requirements. The 3888-bit second type code provides the desired 2 dB coding gain across all modulation schemes while the structured design enables efficient processing that mitigates the time penalty of longer block lengths.
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3/4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.