Clustered QC-LDPC Vertical Layered Decoding With Fewer Memory Accesses
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Solution Overview
Problem
Existing LDPC decoders for QC-LDPC codes face high power consumption due to frequent memory accesses during the decoding process, which affects their efficiency and scalability in low-power applications.
Innovation Solution
The proposed solution involves organizing the parity-check matrix into clusters of circulant permutation matrices (CPMs) and implementing a vertical layered iterative decoder architecture that reduces memory access frequencies by processing multiple CPMs in parallel, using a CNU-Updater module that reads and writes memory less frequently, and employing Pre-Updaters and Sign Accumulators to manage check-node states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional LDPC decoder architecture is used with frequent memory accesses, then decoding accuracy is maintained, but power consumption increases significantly
Solution Approach 1:
The parity-check matrix is segmented into multiple blocks, where each block contains a subset of CPMs. This segmentation allows the decoder to process one block at a time, reducing the amount of data that needs to be held in memory and accessed during each decoding iteration, thereby reducing power consumption while maintaining decoding efficiency
Solution Approach 2:
The CPMs are pre-organized into clusters with specific structural properties that enable efficient processing. The preliminary organization of CPMs into blocks with controlled degrees and patterns allows the decoder to perform computations with reduced memory access requirements from the outset
2Use of energy by moving object
If memory access frequency is reduced to lower power consumption, then power efficiency improves, but decoding speed may be affected
Solution Approach 1:
The decoding process is segmented into multiple iterations, with each iteration processing one block of CPMs. This segmentation reduces memory access frequency within each iteration while the parallel processing capability across blocks maintains overall decoding speed
Solution Approach 2:
The decoder dynamically adjusts its operation by processing blocks in a pipelined manner, where different blocks can be processed at different stages of the decoding process, maintaining high throughput while reducing peak memory access requirements
3Device complexity
If CPMs are organized in clusters for efficient processing, then hardware complexity is reduced, but code design flexibility is constrained
Solution Approach 1:
The clustered CPM structure is designed to be universal, where the same hardware architecture can decode multiple different QC-LDPC codes by reconfiguring the block organization. The multi-functionality is achieved through parameterization of block size, number of blocks, and CPM patterns, allowing the hardware to adapt to different code requirements
Data Source
AI summary
This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.