Quasi-Cyclic LDPC Encoder Architecture for Flexible High-Rate Coding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current encoding devices for LDPC codes face challenges in achieving flexibility and high transmission rates, especially in satellite communication systems where computing components have limited performance.
Innovation Solution
A data encoding device with three encoding circuits for quasi-cyclic LDPC codes, allowing for flexible implementation of different types of LDPC codes and high transmission rates, utilizing a multiplexer circuit architecture and buffer memories for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple types of LDPC codes with different code rates are implemented to provide flexibility, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal encoding device that can encode multiple types of LDPC codes (QC-LDPC, ARA-LDPC, SPC-LDPC) and multiple code rates using a single integrated architecture. The device uses configurable parameters (N, K, M, L, code rate) to adapt to different coding schemes without requiring separate hardware for each code type, thus achieving multi-functionality while controlling complexity.
Solution Approach 2:
The encoding process is segmented into distinct functional blocks: information bit processing, parity bit generation, and output assembly. Each block can be independently configured for different code types. The parallel processing structure divides the encoding task across multiple processing units that can be activated selectively based on the required code type, managing complexity through modular segmentation.
2Productivity
If parallel processing is used to achieve high transmission rates, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the encoding operation into parallel processing blocks that can operate simultaneously. Each block handles a portion of the encoding task (information bits, parity bits, different code rate calculations), allowing the system to achieve high transmission rates through parallel execution while keeping each individual block relatively simple and manageable.
Data Source
AI summary
A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.