QC-LDPC Encoder Architecture for Lower-Power Memory ECC
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Solution Overview
Problem
Current memory systems face challenges in improving memory performance and longevity due to complex and power-consuming error correction code calculations, particularly in low-density parity check (LDPC) encoding processes.
Innovation Solution
The implementation of an efficient hardware architecture for encoding Quasi-Cyclic LDPC codes, combined with a modified RU algorithm, divides the parity check matrix into circulant constructed sparse matrices and reduces the size of dense matrices, minimizing power consumption and calculation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex error correction code calculations are used to improve memory reliability, then correction capability is improved, but power consumption increases
Solution Approach 1:
The parity check matrix H is divided into multiple sub-matrices (H1, H2, H3, H4) with specific structures. This segmentation allows the encoding process to be broken into smaller, more efficient steps that reduce overall computational complexity and power consumption while maintaining the same error correction capability.
Solution Approach 2:
The patent changes the structural parameters of the parity check matrix by using circulant matrices with specific permutation patterns. This parameter optimization reduces the number of non-zero elements and simplifies the encoding calculations, thereby reducing power consumption by approximately 35% while preserving reliability.
2Reliability
If complex error correction code calculations are used to improve memory reliability, then correction capability is improved, but device complexity increases
Solution Approach 1:
The encoding process is segmented into multiple stages corresponding to different sub-matrices. Each stage processes a portion of the data with simplified operations, making the overall complex task manageable and reducing the complexity of individual computational units required in the hardware implementation.
Solution Approach 2:
The patent employs dynamic encoding strategies where the encoding process adapts based on the structured properties of the circulant sub-matrices. This dynamic approach allows the system to exploit the repetitive patterns in the matrix structure to simplify calculations in real-time, reducing overall computational complexity.
3Reliability
If traditional LDPC encoding is used to ensure error correction performance, then correction performance is maintained, but encoding time increases
Solution Approach 1:
The patent pre-structures the parity check matrix into circulant sub-matrices with optimized permutation patterns before the actual encoding process. This preliminary arrangement of matrix elements enables faster encoding operations by reducing the number of computational steps required during real-time data encoding, thus decreasing encoding time while maintaining performance.
Data Source
AI summary
Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.