QC-LDPC Parity Check Matrix for Long-Block 1/2 Rate Encoding
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Solution Overview
Problem
Existing LDPC codes face challenges with high computational intensity due to high-density generator matrices, limiting their practical application, especially in wireless communication systems with block lengths beyond 1944 bits.
Innovation Solution
Implementing quasi-cyclic low-density parity-check (QC-LDPC) codes with a block length of 7776 bits and a code rate of ½, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to simplify encoding and decoding processes, and optimizing the binary matrix Γ for efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density generator matrices are used for LDPC encoding, then error correction capability is improved, but computational complexity increases significantly
Solution Approach 1:
The patent segments the generator matrix into multiple sub-matrices with a specific structure. By dividing the large high-density generator matrix into smaller manageable blocks, the computational burden is reduced while maintaining the error correction capability through the structured arrangement of these sub-matrices.
Solution Approach 2:
The patent applies local quality by creating a quasi-cyclic structure where different sub-matrices have specific properties. The generator matrix is constructed with certain sub-matrices being identity matrices or having specific patterns, allowing efficient computation in certain regions while maintaining overall error correction performance.
2Productivity
If block length is increased beyond 1944 bits to improve communication efficiency, then data transmission capacity is improved, but existing LDPC codes become impractical due to computational intensity
Solution Approach 1:
The patent segments the code into multiple blocks with specific structures. By dividing the long code into manageable segments with quasi-cyclic properties, the system can handle longer block lengths (supporting up to 7776 bits as mentioned in the patent) while keeping computational complexity manageable through the structured approach.
Solution Approach 2:
The patent introduces dynamic properties through the quasi-cyclic structure, where the generator matrix can be efficiently manipulated and transformed. This allows the system to adapt to different block lengths and maintain computational efficiency through the structured dynamics of the code construction.
3Reliability
If complex encoding processes are used to generate parity bits for improved error correction, then reliability is improved, but encoding time and computational resources increase
Solution Approach 1:
The patent applies preliminary action by pre-defining the quasi-cyclic structure of the generator matrix and pre-calculating certain properties of the code. This allows the encoding process to proceed more efficiently during actual transmission, as the structural framework is already established and optimized for fast computation.
Solution Approach 2:
The patent changes the parameters of the encoding process by using a quasi-cyclic structure with specific properties. By transforming the traditional high-density generator matrix into a quasi-cyclic form with controlled density, the system achieves better error correction while reducing the computational parameters required for encoding.
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1/2 and a code block size of 7776 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix. The one or more processors may be configured to encode data using the first binary parity check matrix. The transmitter may be configured to transmit the encoded data.