QC-LDPC Parity Check Matrix Lifting for 7776-Bit 2/3 Codes

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Solution Overview

Problem

Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a maximum block length of 1944 bits for LDPC codes, which restricts the gain in radio channels, particularly in multiple-input and multiple-output channels, and the encoding process for LDPC codes is computationally intensive due to high-density generator matrices.

Innovation Solution

The implementation of quasi-cyclic-low-density parity-check (QC-LDPC) codes with a block length of 7776 bits and a code rate of 2/3, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to generate efficient encoding and decoding processes, allowing for parallel decoding and re-use of existing circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC codes with maximum block length of 1944 bits are used according to existing wireless communication standards, then device compatibility and standard compliance are maintained, but channel performance gain is restricted particularly in MIMO channels

Engineering Contradiction:

Improvechannel performanceVSAvoidblock length flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the block length parameter from the standard maximum of 1944 bits to extended lengths of 3888 bits and 7776 bits, achieving up to four times the length of existing standards. This parameter change enables significantly improved channel performance while maintaining the LDPC code structure through QC-LDPC formulation

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If high-density generator matrices are used for LDPC code encoding, then code rate flexibility is achieved, but computational complexity and encoding intensity increase significantly

Engineering Contradiction:

Improvecode rate flexibilityVSAvoidencoding complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the encoding process by utilizing the quasi-cyclic structure of the parity check matrix, which divides the matrix into smaller circulant submatrices. This segmentation enables more efficient encoding operations while maintaining code rate flexibility through the structured approach

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the traditional mechanical encoding approach using high-density generator matrices with an alternative system based on quasi-cyclic parity check matrices. This substitution reduces computational complexity while preserving the ability to achieve flexible code rates through the structured matrix formulation

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20260012203A1Systems and methods for quasi-cyclic low density parity check (QC-LDPC) code with 2/3 code rate

Publication Date: 2026.01.08 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate R of 2/3, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. The one or more processors may be configured to encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data. In some implementations, the code block size of the second QC-LDPC code may be 7776 bits.