QC-LDPC Parity Matrix Scaling for 7776-Bit 5/6 Code Blocks
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Solution Overview
Problem
Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a block length of 1944 bits, which restricts the gain in radio channels, and LDPC codes with high-density generator matrices are computationally intensive, making them impractical for efficient encoding and decoding.
Innovation Solution
Implementing a quasi-cyclic low-density parity-check (QC-LDPC) code with a block length of 7776 bits and a code rate of 5/6, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to generate efficient encoding and decoding processes, allowing for parallel decoding and re-use of existing circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block length of 1944 bits is used in existing wireless communication standards, then the system maintains compatibility with current standards, but the gain in radio channels is restricted
Solution Approach 1:
The patent embeds the existing 1944-bit block structure within a larger 7776-bit block structure. The 7776-bit block can be viewed as containing four 1944-bit blocks, allowing the system to maintain compatibility with existing standards while achieving extended block length capabilities. This nested structure enables gradual transition and reuse of existing circuitry.
Solution Approach 2:
The patent transitions from a single block length dimension (1944 bits) to multiple block length dimensions by implementing a 7776-bit block structure that can accommodate various code rates (5/6, 4/5, 3/4, etc.). This dimensional expansion allows the system to achieve both longer block lengths and greater versatility in adapting to different communication requirements.
2Reliability
If high-density generator matrices are used for LDPC codes, then encoding and decoding can be performed, but the computational complexity becomes intensive and impractical
Solution Approach 1:
The patent changes the fundamental parameter of the generator matrix from high-density to low-density structure. By using a low-density generator matrix with many zero elements, the computational complexity is dramatically reduced while maintaining the error correction capability. This parameter change transforms an impractical system into an efficient one.
Solution Approach 2:
The patent segments the large 7776-bit block into smaller manageable units and uses a structured low-density generator matrix that can be processed in stages. The quasi-cyclic structure allows the decoding process to be divided into smaller computational tasks, reducing the overall computational burden while maintaining reliability.
3Reliability
If a QC-LDPC code with 7776 bits and 5/6 rate is implemented, then channel performance is significantly enhanced, but the encoding and decoding processes require new circuitry
Solution Approach 1:
The patent designs the QC-LDPC encoding and decoding circuitry to be multi-functional, capable of handling both the new 7776-bit blocks and the existing 1944-bit blocks. The circuitry is designed with universal components that can process different block lengths and code rates, eliminating the need for completely new dedicated hardware and simplifying manufacturing.
Solution Approach 2:
The patent reuses existing decoding circuitry designs for 1944-bit blocks and adapts them for the 7776-bit implementation. By copying and extending proven circuit architectures rather than designing from scratch, the ease of manufacture is significantly improved while maintaining the enhanced channel performance of the longer block length.
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate R of 5/6, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. The one or more processors may be configured to encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data. In some implementations, the code block size of the second QC-LDPC code may be 7776 bits.