QC LDPC Bit Interleaver Layout for Low-Latency Parallel Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to increased latency and limited parallelism, particularly in iterative decoding processes, due to constraints in the number of cyclic blocks and column twisting in the bit interleaver.
Innovation Solution
A bit interleaving method that maps M bits of each constellation to different cyclic blocks and ensures all constellation words are mapped to only those blocks, optimizing the interleaver into N/M parallel sections with section permutations, and applying cyclic block and intra-cyclic-block permutations to improve parallelism and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC LDPC codes, then the system can process codewords, but the interleaving efficiency is low leading to increased latency and limited parallelism
Solution Approach 1:
The bit interleaver is divided into N/M parallel sections, where each section independently processes a subset of cyclic blocks. This segmentation enables concurrent processing of multiple codeword segments simultaneously, increasing interleaving throughput and reducing latency without compromising the quasi-cyclic structure of LDPC codes.
Solution Approach 2:
The patent introduces dynamic column twisting within each parallel section, where the column shift amount varies based on the section index and codeword position. This dynamic adjustment optimizes the interleaving pattern for different sections, improving parallelism while maintaining the required error correction performance of QC LDPC codes.
2Productivity
If the number of cyclic blocks is constrained in the bit interleaver, then the QC LDPC code structure is maintained, but parallelism is limited and processing speed is reduced
Solution Approach 1:
The interleaver is segmented into N/M parallel processing sections, where N is the number of cyclic blocks and M is the modulation order. Each section handles a unique subset of cyclic blocks with independent column twisting, enabling parallel processing while preserving the overall quasi-cyclic LDPC code structure through coordinated output combining.
Solution Approach 2:
Different parallel sections employ locally optimized column twisting patterns specific to their assigned cyclic blocks. This local customization allows each section to operate independently with optimized parameters, increasing parallelism while the global coordination maintains the QC LDPC structural requirements for decoding compatibility.
3Ease of operation
If column twisting is applied in the bit interleaver, then bit permutation is achieved, but the constraint on cyclic blocks limits the degree of permutation and interleaving effectiveness
Solution Approach 1:
Column twisting is implemented dynamically in each parallel section with section-specific shift amounts that vary based on the section index and codeword position. This dynamic column twisting enhances bit permutation capability within each section while the coordinated operation of multiple sections collectively achieves effective interleaving across the entire codeword, overcoming the limitations of static or constrained permutation approaches.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.