QC-LDPC Decoder Parallel Row Updates for Higher Throughput

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Solution Overview

Problem

Conventional methods for decoding quasi-cyclic low-density parity-check (QC-LDPC) codes suffer from insufficient decoding throughput, leading to degraded application performance and lower data transmission rates due to data dependencies between rows in the parity check matrix with circulant weights greater than one.

Innovation Solution

A decoder circuit that processes rows of the parity check matrix in parallel by storing and retrieving row update values for variable nodes with circulant weights greater than one, allowing for parallel processing even in layers with data dependencies, using a belief propagation algorithm such as the sum-product, min-sum, or scaled min-sum algorithm.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional sequential decoding methods are used for QC-LDPC codes with circulant weights greater than one, then decoding accuracy is maintained, but decoding throughput is insufficient and latency is high

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoding latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The parity check matrix is divided into multiple layers, where each layer corresponds to a row of the base matrix. This segmentation allows independent parallel processing of different layers while maintaining the structural properties of QC-LDPC codes, thereby improving throughput without sacrificing decoding accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Row update values are pre-calculated and stored in storage elements before being combined in the layer update unit. This preliminary computation enables subsequent layers to proceed in parallel without waiting for sequential updates, reducing overall decoding latency

Inventive Principle:
Principle #10Preliminary action

2Productivity

If parallel processing of rows is implemented without storage elements, then throughput is improved, but data dependencies between rows with circulant weights greater than one cause processing errors

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoding accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Storage elements act as intermediaries between row process units and the layer update unit. They temporarily hold row update values, ensuring that data dependencies are properly resolved before parallel processing proceeds, thus maintaining decoding accuracy while enabling throughput improvement

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Row update values are pre-calculated and stored in storage elements before being combined in the layer update unit. This preliminary computation enables subsequent layers to proceed in parallel without waiting for sequential updates, reducing overall decoding latency

Inventive Principle:
Principle #10Preliminary action

3Productivity

If hardware parallelization is increased for QC-LDPC decoding, then decoding throughput is improved, but device complexity increases

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoder circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The row process units and layer update unit are designed as universal processing elements that can handle multiple layers and different circulant weights. This multi-functionality allows the same hardware structure to be reused across different decoding operations, improving throughput without proportionally increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The decoder is segmented into modular components (row process units, storage elements, layer update unit) that can be independently configured. This modularity allows flexible parallelization while keeping individual component complexity manageable

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10484012B1Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes
Publication Date: 2019.11.19 XILINX INC
  • US10484012B1 patent drawing
  • US10484012B1 patent drawing
  • US10484012B1 patent drawing

AI summary

A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.