QC-LDPC Parity Matrix Layout for 3888-Bit 1/2-Rate Coding
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Solution Overview
Problem
Existing wireless and wireline communication systems face limitations in achieving efficient encoding and decoding processes for low density parity check (LDPC) codes, particularly with block lengths beyond the 1944 bits supported in 802.11 standards, leading to suboptimal performance in radio channels.
Innovation Solution
Implementing a quasi-cyclic (QC) structure for LDPC codes with a block length of 3888 and a code rate of 1/2, utilizing a parity check matrix and binary matrix to generate a second parity check matrix, which simplifies encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond 1944 bits to improve radio channel gain, then the coding gain increases (about 2 dB in 2x2 MIMO channels), but the complexity of encoding and decoding processes increases
Solution Approach 1:
The parity check matrix H is divided into sub-matrices (HA, HB, HC, HD, HE, TF) with specific structures. Each sub-matrix can be processed independently or in parallel, allowing the large block length code to be decoded through segmented operations rather than treating the entire 3888-bit block as a single unit, thus reducing computational complexity.
Solution Approach 2:
The patent employs a quasi-cyclic structure where the parity check matrix uses cyclic shifts of identity matrices. This dynamic structure allows efficient implementation using shift registers and modular arithmetic, enabling parallel processing and reducing the overall decoding complexity despite the increased block length.
2Reliability
If a code rate of 1/2 is used to improve error correction capability, then more parity bits are generated enhancing reliability, but the transmission efficiency decreases due to higher overhead
Solution Approach 1:
The patent systematically varies the lifting size parameter z (e.g., z=162, z=243) to generate different code rates including 1/2. By changing this fundamental parameter, the same base matrix structure can produce codes with different rates, allowing optimization for specific applications where error correction capability is prioritized over transmission efficiency.
3Reliability
If the block length is extended to 3888 bits to overcome 802.11 standard limitations, then the gain in radio channels improves, but the processing time and computational resources required increase
Solution Approach 1:
The decoding process is segmented into multiple stages corresponding to different sub-matrices of the parity check matrix. Parallel decoding algorithms can process different segments simultaneously, reducing the effective processing time despite the increased block length of 3888 bits.
Solution Approach 2:
The quasi-cyclic structure enables periodic processing patterns where identical computational operations are repeated across different blocks. This regularity allows for optimized instruction pipelines and cache utilization, reducing processing time through efficient resource usage.
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1/2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.