QC-LDPC Vertical Layered Decoding With Predictive Magnitude Maps

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Solution Overview

Problem

Existing vertical layered iterative decoders for quasi-cyclic low-density parity check (QC-LDPC) codes have high computational and storage complexity, which hinders their efficient implementation.

Innovation Solution

The proposed solution simplifies the check-node update processing in vertical layered decoders by using a predictive magnitude map (PMM) function to generate an additional magnitude, reducing the memory requirements and computational complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical layered iterative decoders for QC-LDPC codes are implemented with standard check-node update processing, then decoding accuracy is maintained, but computational complexity and storage requirements increase significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The check-node update processing is segmented into two distinct steps: CNU-Generator step that produces intermediate messages, and CNU-Updater step that updates check node states. This segmentation allows independent optimization of each step, reducing overall computational complexity while preserving decoding accuracy through maintained message passing integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The CNU-Generator step performs preliminary computation of intermediate check-to-variable messages before the CNU-Updater step updates the check node states. By pre-computing these intermediate messages, the decoder reduces the computational burden during the main decoding iteration while ensuring accurate state updates follow.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If vertical layered iterative decoders for QC-LDPC codes are implemented with standard check-node update processing, then decoding accuracy is maintained, but storage complexity increases significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidstorage requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The intermediate check-to-variable messages are extracted and processed separately in the CNU-Generator step, then used to update check node states in the CNU-Updater step. This extraction approach reduces storage requirements by processing messages in stages rather than maintaining all messages simultaneously in memory.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Intermediate messages are generated and prepared in advance during the CNU-Generator step before being used in the CNU-Updater step. This preliminary generation reduces peak memory requirements by eliminating the need to store all intermediate results simultaneously.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If standard check-node update processing is used in vertical layered decoders, then error correction performance is maintained, but resource usage increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidresource usage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The check-node update is divided into CNU-Generator and CNU-Updater steps, allowing more efficient resource allocation. The CNU-Generator can use simpler computation resources for intermediate message generation, while the CNU-Updater uses resources for state updates, reducing overall energy consumption while maintaining error correction performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Intermediate messages are generated preliminarily in the CNU-Generator step using reduced computational resources, then used in the CNU-Updater step. This preliminary generation with lower resource requirements reduces overall energy consumption while preserving the information needed for accurate error correction.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3893399B1Method and apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes with simplified check node processing
Publication Date: 2025.05.28 CODELUCIDA INC
  • EP3893399B1 patent drawingFigure 1
  • EP3893399B1 patent drawingFigure 2
  • EP3893399B1 patent drawingFigure 3

AI summary

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.