QC-LDPC Decoder Circular Shifter Layout for Easier Timing Closure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoders using circular shifters for quasi-cyclic low-density parity check (QC-LDPC) codes face high complexity, leading to computational inefficiency, increased routing congestion, and difficult timing closure, which degrades application performance.
Innovation Solution
The implementation of reduced-complexity circular shifters in LDPC decoders, along with methods to design QC-LDPC codes that operate efficiently with these shifters, by limiting the shift amount and using a threshold value to select shift values for circulant entries in the quasi-cyclic parity check matrix, resulting in increased computational efficiency, decreased routing congestion, and easier timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Sc×Sc circular shifter is used to appropriately shift LLR messages in layered decoding, then the decoding correctness is improved, but the device complexity increases proportionally to ceil(log2(Sc))
Solution Approach 1:
The circular shifter is divided into multiple smaller shifters, each handling a segment of the Sc messages. Instead of one large Sc×Sc shifter, the system uses multiple smaller shifters that operate in parallel or sequence on different segments of the message stream, reducing the complexity of each individual shifter while maintaining overall functionality.
Solution Approach 2:
The patent transforms the problem from a two-dimensional Sc×Sc shifter matrix into a multi-stage sequential process. By introducing time as an additional dimension through multiple clock cycles, the system processes messages in batches across different time steps, effectively reducing the spatial complexity of the shifter hardware.
2Productivity
If the circular shifter complexity is reduced, then computational efficiency and routing congestion are improved, but the ability to appropriately shift all LLR messages may be compromised
Solution Approach 1:
The patent pre-calculates and stores the required shift amounts for different message segments in lookup tables or control registers before the decoding process begins. This preliminary preparation allows the reduced-complexity shifters to quickly apply the correct shifts without requiring complex real-time calculation, maintaining accuracy while reducing hardware complexity.
Solution Approach 2:
The patent introduces control logic and address generation units as intermediaries between the data flow and the simplified shifters. These intermediary components manage the coordination between multiple smaller shifters, ensuring that each message segment is routed to the appropriate shifter and shifted by the correct amount, thereby compensating for the reduced complexity of individual shifters.
Data Source
AI summary
This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.