QC-LDPC Layered Decoder With Zero-Matrix Skipping
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Solution Overview
Problem
Conventional QC-LDPC decoders face challenges with large chip occupation area, high storage demands, complex internal connections, and high power consumption, which hinder decoding efficiency and data throughput.
Innovation Solution
A QC-LDPC decoder architecture that includes a zero matrix monitoring circuit, check node processing circuit, variable node processing circuit, and check circuit, which allows for efficient layered decoding by skipping unnecessary processing steps for zero matrices and determining decoding failure based on update thresholds, thereby optimizing resource usage and improving data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional QC-LDPC decoding is implemented, then decoding performance is achieved, but chip occupation area increases
Solution Approach 1:
The check matrix is divided into multiple layers, and each layer is processed independently through layered decoding. This segmentation allows the decoder to process smaller submatrices sequentially, reducing the simultaneous storage requirements and circuit area compared to processing the entire matrix at once.
Solution Approach 2:
The zero matrix monitoring circuit pre-identifies zero submatrices before the main decoding process. By detecting zero matrices in advance, the system can skip unnecessary processing steps and storage operations, reducing the active circuit area and storage requirements during decoding.
2Reliability
If conventional QC-LDPC decoding is implemented, then decoding performance is achieved, but storage amount increases
Solution Approach 1:
The check matrix is divided into multiple layers, allowing the decoder to store and process only one layer at a time. This reduces the storage requirement from needing to hold the entire check matrix to holding only a fraction of it, proportional to the number of layers.
Solution Approach 2:
After processing each layer, the corresponding data can be discarded from storage before the next layer is processed. The system recovers storage space by discarding processed layer data, allowing efficient reuse of storage resources across multiple layers.
3Reliability
If conventional QC-LDPC decoding is implemented, then decoding performance is achieved, but internal connection complexity increases
Solution Approach 1:
The decoding process is segmented into distinct phases: zero matrix monitoring, check node processing, and variable node processing. Each phase handles specific operations with dedicated circuits, simplifying the internal connections within each module compared to a fully interconnected conventional decoder.
Solution Approach 2:
The zero matrix monitoring circuit performs preliminary detection before data flows to the main processing circuits. This preliminary action allows the system to bypass complex processing paths for zero matrices, simplifying the active connection topology during operation.
4Reliability
If conventional QC-LDPC decoding is implemented, then decoding performance is achieved, but power consumption increases
Solution Approach 1:
The zero matrix monitoring circuit extracts and identifies zero submatrices from the check matrix, allowing the system to remove unnecessary processing operations for those regions. This extraction of useful information (zero matrix locations) enables power savings by disabling processing circuits for zero matrices.
Solution Approach 2:
When zero matrices are detected, the decoder skips the horizontal and vertical phase processing steps for those regions entirely. This skipping of unnecessary operations reduces the active time and power consumption of the processing circuits while maintaining decoding accuracy.
Data Source
AI summary
A QC-LDPC decoder includes: a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix; a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix; a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; and a check circuit, configured to determine whether the variable message satisfies a check standard or not.