Quasi-Cyclic Polar Codes for Parallel Low-Latency Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional polar codes suffer from poor performance due to short cycles in their factor graphs, leading to high computational complexity and decoding latency, making them unsuitable for latency-constrained applications like IoT and M2M communications, and they are not amenable to parallel implementation due to sequential decoding algorithms.

Innovation Solution

The introduction of protograph lifting expansion for polar coding, which eliminates short cycles through hill-climbing optimization of frozen bits allocation and protograph permutation, enabling highly parallelizable decoding and encoding with circulant permutations, resulting in quasi-cyclic polar codes that achieve high coding gain and throughput without increasing computational complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional polar codes use sequential decoding algorithms, then decoding accuracy is maintained, but decoding latency increases and parallel implementation is not feasible

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoding latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the polar code decoding process into multiple independent parallel decoding units, each handling a portion of the codeword. This segmentation enables simultaneous processing of multiple code blocks, thereby increasing decoding throughput and reducing overall latency while maintaining the ability to implement parallel hardware architectures

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic decoding strategies that adapt the decoding process based on channel conditions and code parameters. This includes dynamic adjustment of decoding depth, parallelism level, and resource allocation, allowing the system to optimize between latency and throughput requirements for different application scenarios

Inventive Principle:
Principle #15Dynamics

2Loss of time

If polar codes use short block lengths for low-latency applications, then decoding latency is reduced, but error correction performance deteriorates

Engineering Contradiction:
Improvedecoding latencyVSAvoiderror correction performance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent merges multiple short polar code blocks into a structured parallel decoding framework with inter-block dependencies. By combining several short codes while maintaining their individual advantages, the system achieves low latency from short block lengths while recovering error correction performance through cooperative decoding across multiple blocks

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary processing and pre-computation of decoding parameters before actual decoding occurs. This includes pre-calculating check matrices, preparing parallel decoding paths, and initializing data structures in advance, which reduces the critical path delay and allows short codes to achieve both low latency and good performance

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If QC LDPC codes use larger lifting factor Q to reduce density, then code density decreases and hardware implementation becomes easier, but circuit size and power consumption increase

Engineering Contradiction:
Improvehardware implementation easeVSAvoidcircuit size
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent applies local quality optimization by using different lifting factors Q for different sections or stages of the code. Instead of uniformly increasing Q throughout the entire code structure, the invention selectively applies larger lifting factors only where hardware implementation benefits outweigh the area costs, while using smaller lifting factors in other regions to minimize overall circuit size

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the lifting factor Q as a design parameter based on specific application requirements. By treating Q as a configurable parameter rather than a fixed value, the system can optimize the trade-off between hardware implementation ease and circuit area for different deployment scenarios, code rates, and performance requirements

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4295489B1Protograph quasi-cyclic polar codes and related low-density generator matrix family
Publication Date: 2024.12.25 MITSUBISHI ELECTRIC CORP
  • EP4295489B1 patent drawingFigure 1
  • EP4295489B1 patent drawingFigure 2
  • EP4295489B1 patent drawingFigure 3

AI summary

Data communications and storage systems require error control techniques to be transferred successfully without failure. Polar coding has been used as a state-of-the-art forward error correction code for such an error control technique. However, the conventional decoding based on successive cancellation has a drawback in its poor performance and long latency to complete. Because the factor graph of polar codes has a lot of short cycles, a parallelizable belief propagation decoding also does not perform well. The method and system of the present invention provide a way to resolve the issues by introducing a protograph lifting expansion for a polar coding family so that highly parallelizable decoding is realized to achieve a high coding gain and high throughput without increasing the computational complexity and latency. The invention enables an iterative message passing to work properly by eliminating short cycles through a hill-climbing optimization of frozen bits allocation and permutation.