QC-Polar Decoder Circuit for Variable Code Lengths
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Solution Overview
Problem
Existing communication systems using QC-polar codes require multiple dedicated decoding circuits for different code lengths, leading to an increase in circuit scale and complexity.
Innovation Solution
A decoding device with a likelihood initialization unit, first and second likelihood calculation units, a hard decision unit, and a control unit that iteratively perform likelihood calculations based on code length, allowing for efficient decoding of QC-polar codes with reduced circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dedicated decoding circuits are mounted in parallel for different code lengths, then decoding capability for various code lengths is improved, but circuit scale increases
Solution Approach 1:
The patent implements a universal decoding circuit that can handle multiple code lengths (64, 128, 256, 512 bits) through a single hardware structure. The circuit uses configurable parameters including iteration count (5-15 iterations), block size (64-512 bits), and frozen bit positions to adapt to different code lengths without requiring separate dedicated circuits for each length, thereby maintaining decoding capability across various standards while preventing circuit scale expansion
Solution Approach 2:
The decoding circuit employs dynamic configuration capabilities where the iteration count, block size, and frozen bit positions can be adjusted based on the specific code length being decoded. This dynamic adaptability allows the same hardware to efficiently process different code lengths by reconfiguring its operational parameters rather than requiring static dedicated circuits for each length
2Reliability
If code length of polar code is increased, then error correction performance is improved, but number of dedicated decoding circuits increases
Solution Approach 1:
The patent creates a single universal decoding circuit capable of supporting multiple code lengths from 64 to 512 bits, eliminating the need for separate decoding circuits for each code length. The circuit achieves this through configurable parameters including block size, iteration count, and frozen bit positions that can be adjusted to match different code lengths and their corresponding error correction requirements
Solution Approach 2:
The decoding circuit utilizes parameter changes to adapt to different code lengths and error correction requirements. By adjusting the iteration count (5-15 iterations), block size (64-512 bits), and frozen bit positions based on the specific code length being decoded, the circuit maintains optimal error correction performance across various code lengths without requiring additional hardware
Data Source
AI summary
A decoding device includes a likelihood initialization unit performing initialization process on a storage element for likelihood information used in likelihood calculation of iterative decoding process; a first likelihood calculation unit executing M separate likelihood calculations corresponding to steps 1 to M where M is an integer of 2 or more in likelihood calculation; a second likelihood calculation unit executing M separate likelihood calculations corresponding to steps M+1 to 2M in likelihood calculation of the iterative decoding process; a hard decision unit making hard decision on a likelihood calculation result and generating a decoded bit sequence; a frozen bit removing unit removing a frozen bit and a bit sequence based on a code length of the bit sequence to be decoded from the decoded bit sequence and generating a decoded information bit sequence; and a control unit controlling likelihood calculation of the iterative decoding process.