Quasi-Cyclic Syndrome Decoder Parallel Lookup for Lower Latency
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Solution Overview
Problem
Existing non-volatile memory devices, particularly NAND flash memory, face challenges in achieving efficient error correction with minimal latency due to the inherent unreliability of multi-level NAND flash devices, which requires strong error-correction codes at the expense of additional storage space and increased latency.
Innovation Solution
The implementation of a quasi-cyclic syndrome-based decoder that reduces latency by computing a syndrome from a noisy codeword, generating memory cell addresses based on the syndrome, reading error patterns in parallel, and determining a candidate codeword using checksums, leveraging the structure of the quasi-cyclic parity check matrix for efficient error location computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong error-correction codes are used to improve data reliability, then error correction capability is improved, but decoding latency increases
Solution Approach 1:
The decoder is divided into multiple parallel processing units that simultaneously process different portions of the codeword. Each processing unit handles a specific segment of the decoding task, allowing concurrent execution of syndrome computation, error pattern identification, and correction operations, thereby reducing overall decoding latency while maintaining strong error correction capability
Solution Approach 2:
Error patterns are pre-computed and stored in lookup tables during the design phase. During actual decoding operations, the system performs preliminary syndrome computation and directly retrieves pre-computed error patterns from memory, avoiding time-consuming iterative error correction calculations and significantly reducing decoding latency
2Reliability
If strong error-correction codes are used to improve data reliability, then error correction capability is improved, but additional storage space for ECC parity bits is required
Solution Approach 1:
The system employs quasi-cyclic LDPC codes with specific parameter configurations that optimize the balance between error correction capability and code rate. By carefully selecting code parameters such as block length, dimension, and quasi-cyclic structure, the system achieves strong error correction performance while minimizing the overhead of parity bits relative to data bits
Data Source
AI summary
Disclosed are devices, systems and methods for reducing the latency of a quasi-cyclic linear code decoder. An example method includes receiving a noisy codeword, the codeword having been generated from a quasi-cyclic linear code and provided to a communication channel prior to reception by the decoder; computing a syndrome based on the noisy codeword; generating a plurality of memory cell addresses, a first memory cell address being a function of the syndrome and subsequent memory cell addresses being within a predetermined address range of the function of the syndrome; reading, in a parallel manner to reduce the latency of the decoder, a plurality of error patterns from the plurality of memory cell addresses and computing a checksum for each of the plurality of error patterns; and determining, based on the checksum for each of the plurality of error patterns, a candidate version of the transmitted codeword.