QC-LDPC Bit Interleaving with Sectioned Cyclic Block Permutation
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, with each constellation word comprising bits from multiple cyclic blocks, ensuring all bits of a section are mapped to only Q constellation words, and applying specific permutation processes to optimize bit mapping and parallelism, such as section permutation and cyclic block permutation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The codeword is divided into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized in a structured manner, enabling efficient parallel processing by ensuring that each section can be independently processed without requiring the total number of cyclic blocks to be a multiple of the interleaver matrix columns.
Solution Approach 2:
The patent employs dynamic permutation processes including section permutation and cyclic block permutation. These dynamic operations allow flexible reorganization of bits within sections and across cyclic blocks, optimizing parallelism and reducing latency adaptively based on the codeword structure without rigid constraints on block counts.
2Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is limited due to restricted interleaver configurations
Solution Approach 1:
By dividing the codeword into sections with specific numbers of cyclic blocks, the patent enables independent parallel processing of each section. This segmentation removes the constraint that the total number of cyclic blocks must be a multiple of interleaver matrix columns, allowing more flexible and parallel interleaver configurations.
Solution Approach 2:
The patent implements dynamic permutation mechanisms including section permutation that can independently rearrange sections, and cyclic block permutation that can independently rearrange cyclic blocks within sections. These dynamic operations increase parallelism by allowing simultaneous permutation operations across multiple sections without rigid configuration constraints.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each is made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.