QC-LDPC Bit Interleaver Layout for Parallel BICM Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bit interleavers in BICM systems, such as those used in the DVB-T2 standard, face issues with impaired parallelism and limited configuration options due to non-multiple cyclic block counts, leading to increased latency and suboptimal performance, especially in iterative decoding scenarios.
Innovation Solution
A bit interleaving method that maps M bits of each constellation to different cyclic blocks and ensures all constellation words are mapped to specific cyclic blocks, optimizing the interleaver into N/M parallel sections with section permutations, enhancing parallelism and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleavers are used in BICM systems with QC-LDPC codes, then the system can operate with standard configurations, but parallelism is impaired and latency increases when cyclic block counts are non-multiples
Solution Approach 1:
The interleaver is divided into multiple parallel sections, where each section processes a subset of cyclic blocks independently. This segmentation enables concurrent processing of multiple data streams, thereby improving parallelism and reducing overall latency in the interleaving operation.
Solution Approach 2:
The patent modifies the interleaver configuration parameters (number of sections, sections per cyclic block) to optimize performance for specific code rates and block lengths. By adjusting these parameters, the system achieves better parallelism and reduced latency while maintaining compatibility with QC-LDPC code structures.
2Adaptability or versatility
If conventional bit interleavers are used, then implementation is straightforward, but configuration options are limited and performance in iterative decoding is suboptimal
Solution Approach 1:
The interleaver design allows dynamic configuration of sections per cyclic block based on the specific QC-LDPC code parameters (code rate, block length). This dynamic adaptability enables the system to optimize interleaving performance for different decoding scenarios, improving reliability in iterative decoding while maintaining implementation flexibility.
Solution Approach 2:
The patent presents a universal interleaver framework that can accommodate various QC-LDPC code configurations and BICM system parameters. By designing the interleaver to work with different code rates and block lengths through parameter adjustment, it provides multi-functional capability that improves both adaptability and decoding performance across diverse applications.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme, including a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the bit interleaving method comprising: a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; and a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, wherein N is a multiple of M, according to the bit permutation rule, MxQ bits of the codeword are written into an M by Q matrix row-by-row and the written MxQ bits of the codeword are read from the M by Q matrix column-by-column.