QC-LDPC Bit Interleaver Layout for Non-Multiple Cyclic Blocks
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Solution Overview
Problem
Conventional bit interleavers for bit-interleaved coded modulation with quasi-cyclic low-density parity-check codes face inefficiencies due to impaired parallelism and limited configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, leading to increased latency and suboptimal performance in iterative decoding.
Innovation Solution
A bit interleaving method and corresponding interleaver that maps M bits of each constellation to different cyclic blocks and ensures all constellation words are mapped to specific cyclic blocks, optimizing the interleaving process to improve parallelism and reduce latency, while also applying cyclic block permutations to enhance mapping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleavers are used with fixed matrix column configurations, then device structure is simplified, but interleaving efficiency deteriorates when the number of cyclic blocks is not a multiple of matrix columns
Solution Approach 1:
The patent implements dynamic configuration of the interleaver matrix columns based on the number of cyclic blocks in the QC-LDPC code. The interleaver adapts its structure by setting the number of columns equal to the number of cyclic blocks, allowing efficient processing regardless of whether the cyclic block count is a multiple of traditional fixed column configurations. This dynamic adaptation resolves the contradiction by maintaining high interleaving efficiency while avoiding the need for complex padding or truncation operations.
2Loss of time
If fixed interleaver matrix configurations are used, then implementation is simpler, but latency increases due to impaired parallelism
Solution Approach 1:
The patent segments the interleaving process into independent column operations where each column corresponds to a cyclic block. By organizing the interleaver matrix with columns equal to the number of cyclic blocks, the system enables parallel processing of multiple cyclic blocks simultaneously. This segmentation approach reduces latency by allowing concurrent interleaving operations across different cyclic blocks while maintaining a relatively simple matrix-based structure.
3Reliability
If conventional interleaving mappings are used, then mapping rules are simpler, but bit-error rate performance deteriorates in iterative decoding
Solution Approach 1:
The patent applies local quality optimization by implementing specific permutation patterns within each column of the interleaver matrix that correspond to different cyclic blocks. Each column can have optimized permutation characteristics tailored to the properties of its associated cyclic block, improving the overall bit-error rate performance. This localized optimization approach enhances reliability while keeping the global structure relatively simple through the matrix framework.
Data Source
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AI summary
Bit interleaving method for interleaving a QC-LDPC codeword made up of N cyclic blocks each consisting of Q cyclic block bits and the constellation word being made up of M bits with N being not a multiple of M. The bit interleaving comprises a cyclic block permutation step, a bit permutation step and a dividing step, where a first rule is applied to the N-N' cyclic blocks, with N' = N -X and X = rem(N, M) and a second rule is applied to the X cyclic blocks. After the cyclic block permutation process and according to the first rule, the N' cyclic blocks are divided so that the Q bits in each of the N' cyclic block are each allocated to a bit of an identical bit index in Q constellation words and the Q constellation words are each made up of one bit from each of M different cyclic blocks, said M different cyclic blocks being common to said Q constellation words.