QC-LDPC Bit Interleaving Layout for Parallel Constellation Mapping
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, where each constellation word includes bits from multiple cyclic blocks, ensuring all bits of a section are mapped to only Q constellation words associated with that section, and applies a bit permutation process to optimize the mapping of LDPC codeword bits onto constellation bits, enhancing parallelism and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The patent segments the QC-LDPC codeword into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be divided into independent parallel operations on each section, improving throughput and reducing latency by eliminating the bottleneck caused by non-multiples of interleaver matrix columns.
Solution Approach 2:
The patent introduces a section dimension in addition to the traditional row-column interleaving structure. By organizing codeword bits into sections with multiple cyclic blocks and applying permutation within each section, the system adds a dimensional layer that enables parallel processing and resolves the latency issue when cyclic block count is not a multiple of matrix columns.
2Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but the configuration options are limited and parallelism is reduced
Solution Approach 1:
The patent employs dynamic permutation patterns within each section, allowing the interleaver to adapt its configuration based on the number of cyclic blocks and system requirements. The permutation rules can be adjusted to match different code rates and block sizes, providing flexibility without requiring complete redesign of the interleaver structure.
Solution Approach 2:
The patent creates a universal interleaving framework that can handle various QC-LDPC configurations through the section-based structure. The same interleaver design works for different numbers of cyclic blocks, code rates, and constellation sizes by adjusting the permutation parameters within sections, eliminating the need for multiple specialized interleavers.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.