QC-LDPC Bit Interleaving for Parallel Constellation Mapping

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Solution Overview

Problem

Existing bit-interleaved coding and modulation (BICM) systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks in the LDPC codeword is not a multiple of the number of columns in the bit interleaver matrix, leading to impaired parallelism and increased latency, especially in iterative decoding.

Innovation Solution

A bit interleaving method that applies a bit permutation process to quasi-cyclic low-density parity-check codes, dividing the codeword into constellation words and performing intra-cyclic-block permutations to optimize the mapping of bits onto constellations, ensuring each constellation word is associated with multiple cyclic blocks and mapped to specific sections, thereby improving parallelism and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of cyclic blocks is not a multiple of the number of columns in the bit interleaver matrix, then the interleaving can be applied to QC LDPC codes, but parallelism is impaired and latency increases

Engineering Contradiction:
Improveadaptability to QC LDPC codesVSAvoidparallelism and latency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent divides the codeword into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to handle cases where the total number of cyclic blocks is not a multiple of the interleaver columns, by processing each section independently and ensuring proper mapping within each section while maintaining overall parallelism.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If conventional bit interleaving is applied to QC LDPC codes, then bit interleaving can be performed, but the mapping efficiency onto constellations is reduced

Engineering Contradiction:
Improvebit interleaving operationVSAvoidmapping efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies different permutation rules to different sections of the codeword. Specifically, it performs intra-cyclic-block permutation within each section and inter-section permutation between sections, allowing each part of the data to be optimized for its specific mapping requirements while maintaining overall system efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a two-dimensional mapping approach where bits are first organized into sections (one dimension) and then mapped to constellation words (another dimension). This dimensional organization improves mapping efficiency by ensuring that bits from different cyclic blocks are properly distributed across constellation points.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10361726B2Parallel bit interleaver
Publication Date: 2019.07.23 PANASONIC HOLDINGS CORP
  • US10361726B2 patent drawing
  • US10361726B2 patent drawing
  • US10361726B2 patent drawing

AI summary

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.