QC-LDPC Decoder Architecture for Multi-Standard Parallel Throughput
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Solution Overview
Problem
Conventional LDPC decoders require significant silicon area and inefficiencies due to the need for multiple processors and hardware components to accommodate various wireless communication standards, leading to restricted throughput and increased hardware requirements.
Innovation Solution
A multi-standard LDPC decoder architecture that reuses data paths, RAM, and logic circuits to process multiple smaller code words simultaneously, using a circular shifter to address unused data paths and reduce RAM access contentions, allowing for efficient processing of matrices of various sizes and standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate LDPC decoders are used to support different wireless communication standards, then each standard can be processed correctly, but the silicon area consumed increases significantly
Solution Approach 1:
The patent implements a universal LDPC decoder architecture that can process multiple wireless communication standards (5G NR, Wi-Fi, DVB, etc.) using a single hardware structure. The decoder uses configurable parameters including variable node updater count (VNU_COUNT), check node updater count (CNU_COUNT), and submatrix size (ZC) to adapt to different standards without requiring separate dedicated decoders for each standard, thereby reducing overall silicon area while maintaining multi-standard support
Solution Approach 2:
The patent segments the LDPC decoding process into independent variable node updating (VNU) and check node updating (CNU) modules that can be configured in different quantities and arrangements. By dividing the decoder into these functional segments with configurable parallel instances, the system can optimize the number of each module type based on the specific standard being processed, enabling flexible adaptation to different standards with a single hardware platform
2Productivity
If multiple parallel CNU and VNU processors are used to increase throughput, then system throughput requirements are met, but data dependency and RAM access collisions restrict the number of parallel processors
Solution Approach 1:
The patent implements a two-phase processing approach where check node updating (CNU) is performed first to generate updated check node data, which is then stored in memory before variable node updating (VNU) begins. This preliminary completion and storage of CNU results eliminates data dependency conflicts during parallel processing, allowing multiple CNU and VNU processors to operate simultaneously without coordination complexity, thereby enabling higher throughput
3Productivity
If multiple parallel CNU and VNU processors are used to increase throughput, then processing capacity increases, but RAM access collisions increase
Solution Approach 1:
The patent stores the complete set of check node data in memory after CNU processing completes, before VNU processing begins. This preliminary storage creates a stable data foundation that eliminates the need for multiple processors to simultaneously access and update the same memory locations, thereby preventing RAM access collisions even when multiple parallel VNU processors are used to increase processing capacity
Data Source
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AI summary
A wireless receiving device comprises a quasi-cyclic low-density parity check (QC-LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.