QC-LDPC Decoder RCQ Circuit for Low-Bit-Width Storage Decoding

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Solution Overview

Problem

Existing decoding methods in storage devices face challenges with limited resources, leading to degraded performance, increased time, and inaccuracies in estimating original information bits, resulting in slower processes and higher decoding failures.

Innovation Solution

Implementing a Reconstruction-Computation-Quantization (RCQ) approach in a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder, which uses layer-specific reconstruction and quantization functions to improve decoder performance by efficiently processing messages and tracking probability densities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If limited resources are allocated to the decoder, then device complexity is reduced, but decoding accuracy and speed deteriorate

Engineering Contradiction:
Improvedecoder resource allocationVSAvoiddecoding accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The decoding process is segmented into multiple layers with different bit-width precisions. Less critical computations use lower bit-width (reducing resource usage), while critical path computations use higher bit-width (maintaining accuracy). This layering allows the decoder to achieve high reliability without requiring all resources to operate at maximum precision simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the decoding computation are assigned different quality levels (bit-width precisions) based on their importance to the final result. Critical computations receive higher precision resources, while less critical computations use lower precision, optimizing the overall balance between resource usage and decoding accuracy.

Inventive Principle:
Principle #3Local quality

2Device complexity

If limited resources are allocated to the decoder, then device complexity is reduced, but decoding speed decreases

Engineering Contradiction:
Improvedecoder resource allocationVSAvoiddecoding speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The decoder is divided into layers that can be processed in parallel, with each layer handling specific computations at different precision levels. This segmentation enables pipelining and parallel processing, improving throughput without requiring all resources to operate at full capacity simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder dynamically adjusts the precision level used for different computations based on their criticality and the current decoding state. This dynamic resource allocation allows the system to maintain high decoding speed by using appropriate precision levels rather than consistently using maximum precision for all operations.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If lower precision is used in decoding, then resource usage is reduced, but decoding accuracy deteriorates

Engineering Contradiction:
Improveresource usageVSAvoidinformation bit estimation accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

Different computational stages and message types are assigned different precision levels based on their impact on final decoding accuracy. Critical path computations and messages that significantly influence the result use higher precision, while less critical computations use lower precision, optimizing the overall accuracy-resource tradeoff.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The precision parameter (bit-width) is varied across different layers and computational stages of the decoder. By changing the precision parameter locally rather than uniformly, the system achieves high overall accuracy while reducing total resource consumption compared to using maximum precision throughout.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11316541B2Low-density parity-check (LDCP) decoder of reconstruction-computation-quantization (RCQ) approach for a storage device
Publication Date: 2022.04.26 SAMSUNG ELECTRONICS CO LTD
  • US11316541B2 patent drawing
  • US11316541B2 patent drawing
  • US11316541B2 patent drawing

AI summary

A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.