QC-LDPC Encoder Hardware Sharing Across Code Lengths and Rates
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Solution Overview
Problem
Existing LDPC encoders face high complexity and large memory requirements due to the need for complex hardware and extensive storage for backward substitution procedures, especially when implementing different block lengths and code rates, which complicates the encoding process and hardware implementation.
Innovation Solution
The proposed solution involves a parity check encoder that shares hardware resources among different block lengths and code rates by exploiting common sub-expressions in the parity check matrices, reducing storage and hardware complexity through the use of shared XOR hardware resources and a two-step encoding algorithm that computes parity bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backward substitution procedure is implemented for LDPC codes with different block lengths and code rates, then encoding flexibility is improved, but hardware complexity and memory requirements increase significantly
Solution Approach 1:
The patent implements a universal encoder architecture that can handle multiple LDPC code configurations (different block lengths and code rates) using the same hardware resources. The encoder uses a unified backward substitution procedure that adapts to different code parameters without requiring separate hardware implementations for each code type, thereby achieving multi-functionality while controlling hardware complexity.
Solution Approach 2:
The patent changes the approach from storing multiple complete parity check sub-matrices for different codes to storing only the non-zero element positions and values as compact parameter representations. This parameter-based representation allows the same hardware to efficiently encode different LDPC codes by loading appropriate parameter sets, reducing memory requirements while maintaining encoding flexibility.
2Manufacturing precision
If non-zero elements for multiple sub-matrices are stored for different code lengths and rates, then encoding accuracy is improved, but memory storage requirements increase
Solution Approach 1:
The patent extracts only the essential non-zero elements from the parity check sub-matrices and stores them in a compact format. Instead of storing complete sub-matrices with all their elements (including zeros), the implementation extracts and stores only the critical non-zero elements along with their positions, significantly reducing memory storage requirements while preserving encoding accuracy.
Solution Approach 2:
The patent performs preliminary processing of the parity check matrices to identify and store only the non-zero elements before the actual encoding process. This preliminary action of pre-processing and compacting the matrix data reduces the memory burden during encoding operations while ensuring that all necessary information for accurate encoding is preserved.
3Adaptability or versatility
If complex hardware is used to implement backward substitution for multiple codes, then encoding capability is improved, but hardware resource requirements increase
Solution Approach 1:
The patent merges the encoding capabilities for multiple LDPC codes into a single unified hardware implementation. The backward substitution procedure is implemented as a universal algorithm that can process different code types using the same computational resources, thereby improving encoding capability across multiple codes without proportionally increasing hardware resource requirements.
Solution Approach 2:
The encoder is designed as a universal multi-functional device that can encode various LDPC code configurations. By implementing a single hardware architecture that adapts to different codes through parameter loading rather than dedicated hardware for each code, the patent achieves enhanced encoding capability while controlling hardware resource consumption.
Data Source
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AI summary
The present invention is directed toward a parity check encoder for low density parity check (LDPC) codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix corresponding to the message bits; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes. Thus, the same encoder hardware can perform encoding for different block lengths and/or code rates using reduced storage and hardware complexity requirements.