QC-LDPC Bit Interleaving with Folding Sections for Parallel Decoding
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks is not a multiple of the bit interleaver's columns, leading to impaired parallelism and increased latency, especially in iterative decoding processes.
Innovation Solution
A bit interleaving method that divides codewords into folding sections, applying a bit permutation process to map M bits from multiple cyclic blocks into constellation words, ensuring all bits in a folding section are mapped to only Q/F constellation words, thereby optimizing interleaving and reducing latency while enhancing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be completed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the interleaver columns
Solution Approach 1:
The patent divides the codeword into multiple folding sections, where each folding section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the contradiction by structuring the data to enable parallelism while handling cases where the total number of cyclic blocks is not a multiple of the interleaver columns.
Solution Approach 2:
The patent introduces a folding factor F that creates an additional dimension in the interleaving structure. By organizing cyclic blocks into folding sections and using the folding factor to determine how many cyclic blocks form one folding section, the system transforms the traditional single-dimension interleaving into a multi-dimensional structure that enables parallel processing and reduces latency.
2Adaptability or versatility
If the number of cyclic blocks is not a multiple of the interleaver columns, then flexibility in system design is maintained, but parallelism is impaired
Solution Approach 1:
The patent makes the interleaving structure dynamic by introducing the folding factor F as a configurable parameter. The number of folding sections and the composition of each folding section can be adjusted based on the specific system requirements and the relationship between the number of cyclic blocks and interleaver columns. This dynamic structure allows the system to maintain flexibility while optimizing for parallelism in different operating conditions.
Solution Approach 2:
The patent changes the structural parameters of the interleaving process by defining folding sections with a specific number of cyclic blocks determined by the folding factor. This parameter change transforms the fixed interleaving structure into a flexible one that can adapt to different numbers of cyclic blocks while maintaining parallelism through the organized folding section structure.
3Ease of manufacture
If traditional interleaving methods are used, then implementation is straightforward, but latency increases in iterative decoding processes
Solution Approach 1:
By segmenting the codeword into folding sections that can be independently processed, the patent enables parallel execution of interleaving operations across multiple sections. This segmentation maintains implementation simplicity through the regular structure of folding sections while significantly reducing decoding latency by eliminating sequential processing bottlenecks.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.