QC-LDPC Bit Interleaving Across Folding Sections and Cyclic Blocks

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Solution Overview

Problem

Existing bit-interleaved coding and modulation (BICM) systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks in the LDPC codeword is not a multiple of the number of columns in the bit interleaver matrix, leading to impaired parallelism and increased latency, especially in iterative decoding.

Innovation Solution

A bit interleaving method that applies a bit permutation process to quasi-cyclic low-density parity-check codes, dividing the codeword into constellation words and performing intra-cyclic-block permutations to optimize the mapping of bits onto constellations, ensuring each constellation word is associated with multiple cyclic blocks and mapped efficiently across sections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the number of columns in the bit interleaver matrix

Engineering Contradiction:
Improveinterleaving efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The codeword is divided into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the issue of impaired parallelism when the total number of cyclic blocks is not a multiple of the matrix columns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a two-dimensional structure with sections and columns, where bits are arranged in a matrix format with sections as rows and columns as columns. This dimensional organization enables efficient parallel processing by allowing simultaneous access and manipulation of multiple bits across different sections, thereby reducing latency while maintaining interleaving efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but parallelism is impaired

Engineering Contradiction:
Improveinterleaving efficiencyVSAvoidparallelism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By dividing the codeword into multiple sections with a predetermined number of cyclic blocks each, the patent creates a segmented structure that facilitates parallel processing. Each section can be independently processed, maintaining high parallelism even when the total number of cyclic blocks does not evenly divide by the matrix columns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the interleaving process by introducing section-based organization and specific mapping rules between sections and columns. This parameter change enables the system to maintain optimal parallelism by ensuring that each section's bit distribution across columns follows a pattern that maximizes parallel processing capability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If bit permutation is applied to optimize constellation word mapping, then receiver performance and BER improve, but the complexity of the interleaving process increases

Engineering Contradiction:
Improvereceiver performanceVSAvoidinterleaving process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bit permutation process is applied separately to each section rather than to the entire codeword at once. This segmentation of the permutation operation reduces the overall complexity by breaking down a large complex transformation into multiple smaller, more manageable transformations that can be executed efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies bit permutation within each section as a preliminary action before the final constellation word mapping. This preliminary permutation optimizes the bit distribution in advance, ensuring that subsequent mapping operations produce optimal receiver performance without requiring complex real-time adjustments during the main processing stage.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10886946B2Parallel bit interleaver
Publication Date: 2021.01.05 PANASONIC HOLDINGS CORP
  • US10886946B2 patent drawing
  • US10886946B2 patent drawing
  • US10886946B2 patent drawing

AI summary

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.