QC-LDPC Bit Interleaver Layout for Parallel Folding Sections
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks is not a multiple of the bit interleaver's columns, leading to impaired parallelism and increased latency, especially in iterative decoding processes.
Innovation Solution
A bit interleaving method that permutes bits in quasi-cyclic low-density parity-check codes by dividing codewords into constellation words and selecting a subset of cyclic blocks such that the number of selected blocks is a multiple of the divisor of the number of bits per constellation, ensuring that each constellation word includes bits from multiple cyclic blocks and is mapped to specific folding sections, thereby optimizing interleaving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cyclic blocks is not a multiple of the bit interleaver's columns, then the interleaving can be applied to all cyclic blocks, but parallelism is impaired and latency increases
Solution Approach 1:
The patent divides the codeword into multiple folding sections, where each folding section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the contradiction between processing all blocks and maintaining parallelism.
Solution Approach 2:
The patent dynamically adjusts the number of folding sections and the distribution of cyclic blocks across sections based on the relationship between the number of cyclic blocks and the bit interleaver's columns. This dynamic configuration enables the system to optimize parallelism while ensuring all cyclic blocks are processed.
2Productivity
If the number of cyclic blocks is not a multiple of the bit interleaver's columns, then the interleaving can be applied to all cyclic blocks, but parallelism is impaired
Solution Approach 1:
By segmenting the codeword into folding sections with controlled sizes, the patent enables parallel processing within each section while maintaining overall system efficiency. The segmentation strategy ensures that the number of cyclic blocks in each section is compatible with the bit interleaver's column structure.
Solution Approach 2:
The patent changes structural parameters such as the number of folding sections and the distribution of cyclic blocks across sections to optimize parallelism. By adjusting these parameters based on the input codeword characteristics, the system maintains high interleaving efficiency without impairing parallelism.
3Productivity
If bits are permuted across multiple cyclic blocks for each constellation word, then interleaving efficiency is improved, but the mapping complexity increases
Solution Approach 1:
The patent segments the bit permutation process into folding sections, where each section handles a specific subset of cyclic blocks. This segmentation simplifies the mapping complexity by localizing the permutation operations within manageable sections while maintaining overall interleaving efficiency.
Solution Approach 2:
The patent applies different permutation strategies to different folding sections based on their specific characteristics. By tailoring the mapping approach to each section's requirements, the system improves interleving efficiency without uniformly increasing complexity across the entire system.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.