QC-LDPC Bit Interleaver Layout for Parallel Low-Latency Mapping
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, where each constellation word includes bits from multiple cyclic blocks, ensuring all bits of a section are mapped to only Q constellation words associated with that section, and applying a bit permutation process to optimize the mapping of cyclic blocks to constellation words, thereby enhancing parallelism and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The codeword is divided into N/M sections, where each section contains M cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the inefficiency when the number of cyclic blocks is not a multiple of interleaver matrix columns.
Solution Approach 2:
The patent introduces a two-dimensional organization of cyclic blocks into sections, where each section is associated with specific constellation words. This dimensional reorganization enables parallel processing by mapping bits from M different cyclic blocks within a section to Q constellation words, improving productivity while controlling latency.
2Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but parallelism is limited due to configuration constraints
Solution Approach 1:
The patent creates a universal interleaving framework where N cyclic blocks are divided into N/M sections, and each section can be independently processed. This multi-functional structure allows the same interleaving mechanism to handle various code lengths and rates by simply adjusting N and M, enhancing both parallelism and configuration flexibility.
Solution Approach 2:
The interleaver configuration is made dynamic by allowing flexible division of cyclic blocks into sections. The parameter M can be adjusted to optimize parallelism for different scenarios, enabling the system to adapt to various code rates and block sizes while maintaining efficient parallel processing.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.