QC-LDPC Base Matrix Layout for High-Speed Layered Decoding
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Solution Overview
Problem
Existing LDPC decoding and encoding methods face inefficiencies due to long waiting times and complex hardware requirements, particularly in high-bit-rate scenarios where layered decoding is used.
Innovation Solution
The proposed solution involves determining a basic matrix with specific up-and-down adjacent pairs for LDPC encoding and decoding, allowing for high pipeline speed and reducing the need for complex hardware, such as inverse cyclic shift networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional layered decoding is used for LDPC codes, then decoding capability is achieved, but long waiting times occur and hardware complexity increases
Solution Approach 1:
The patent segments the basic matrix into multiple sub-matrices arranged in a specific structure with up-and-down adjacent pairs. This segmentation allows the decoding process to be divided into independent parallel operations, eliminating long waiting times while maintaining decoding capability through the structured arrangement of sub-matrices.
Solution Approach 2:
The patent introduces a new structural dimension by organizing sub-matrices in a two-dimensional array with specific up-and-down adjacent pair relationships. This dimensional organization enables parallel processing across multiple dimensions, reducing waiting time while preserving the decoding capability through the structured matrix arrangement.
2Reliability
If conventional LDPC encoding and decoding hardware is implemented, then encoding and decoding functions are achieved, but hardware complexity increases
Solution Approach 1:
The basic matrix is segmented into multiple sub-matrices that can be processed independently. This segmentation reduces hardware complexity by allowing modular implementation where each sub-matrix can be handled by simpler, dedicated hardware units rather than requiring complex universal processing units.
Solution Approach 2:
The structured basic matrix with up-and-down adjacent pairs enables a single hardware unit to perform multiple functions by processing different sub-matrices in sequence or parallel. This multi-functionality reduces overall hardware complexity while maintaining complete encoding and decoding capabilities.
3Productivity
If high pipeline speed is achieved through optimized basic matrix structure, then encoding and decoding efficiency is improved, but hardware complexity may increase
Solution Approach 1:
The basic matrix is divided into sub-matrices arranged in a structured pattern with up-and-down adjacent pairs. This segmentation enables high pipeline speed by allowing parallel processing of multiple sub-matrices simultaneously, improving encoding and decoding efficiency without requiring overly complex hardware since each sub-matrix can be processed by simple, identical units.
Data Source
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AI summary
An encoding method, decoding method, encoding device and decoding device for structured LDPC codes. The method includes: determining a base matrix used for encoding, which includes K0 up-and-down adjacent pairs; and according to the base matrix and an expansion factor corresponding to the base matrix, performing an LDPC encoding operation of obtaining a codeword of Nb×z bits according to source data of (Nb-Mb)×z bits, herein z is the expansion factor, and z is a positive integer which is greater than or equal to 1. The provided technical solution is applicable to the encoding and decoding of the structured LDPC, thereby realizing the encoding and layered decoding of LDPC at the high pipeline speed.