QC-LDPC Bit Interleaver Layout for Parallel Low-Latency Mapping
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, with each constellation word comprising bits from multiple cyclic blocks, ensuring all bits of a section are mapped to only Q constellation words, and applying specific permutation processes to optimize bit mapping and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The patent segments the QC-LDPC codeword into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be divided into independent parallel operations on each section, improving throughput and reducing latency by eliminating the bottleneck caused by non-multiples of interleaver matrix columns.
Solution Approach 2:
The patent introduces a new dimension to the interleaving structure by organizing bits into sections with multiple rows and columns, where each section can be independently processed. This dimensional organization allows for parallel processing across sections while maintaining the required interleaving properties, thereby improving productivity without increasing latency.
2Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but the configuration options are limited and parallelism is reduced
Solution Approach 1:
The patent creates a universal interleaving structure that can accommodate different codeword lengths, cyclic block numbers, and constellation sizes through configurable section divisions. This multi-functional design allows the same interleaver architecture to be adapted to various QC-LDPC configurations without requiring separate dedicated interleavers for each case, thereby enhancing adaptability while managing complexity.
Solution Approach 2:
The patent introduces dynamic configurability to the interleaver by allowing the number of sections, rows, and columns to be adjusted based on the specific QC-LDPC code parameters and system requirements. This dynamic structure enables optimal parallelism to be achieved for different configurations without increasing device complexity, as the same hardware can be reconfigured for different operating conditions.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.