QC-LDPC Decoder Permutation Circuit With Fewer Routing Layers
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Solution Overview
Problem
The existing permutation networks for QC-LDPC decoders in storage devices face challenges with increased size, leading to longer processing cycles, higher power consumption, and increased hardware costs due to the complexity of placing chips and routing wires, which hampers decoding efficiency.
Innovation Solution
A permutation network designing method that reduces the number of selectors and routing wires by identifying a target permutation layer to be removed from the first permutation network, constructing a second permutation network, and optimizing the placement of selectors and routing wires based on the check matrix of the QC-LDPC decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full sized multilayer permutation network is implemented, then decoding coverage is improved, but device complexity and hardware cost increase
Solution Approach 1:
The patent extracts and removes redundant permutation layers from the full-sized permutation network. Specifically, it identifies and eliminates permutation layers that do not contribute to decoding performance, thereby reducing the network size while maintaining essential decoding coverage.
Solution Approach 2:
The patent segments the permutation network into multiple layers and selectively retains only the necessary layers for effective decoding. This segmentation allows the system to maintain the beneficial structure of layered permutation networks while removing unnecessary complexity.
2Reliability
If a larger permutation network is used, then decoding accuracy is improved, but processing time increases
Solution Approach 1:
The patent removes redundant permutation layers that increase processing time without contributing to decoding accuracy. By extracting only the essential layers needed for accurate decoding, the system achieves a balance between accuracy and speed.
Solution Approach 2:
The patent applies partial action by implementing only the necessary permutation layers required for decoding accuracy, rather than using the complete full-sized network. This partial implementation suffices for achieving the required decoding performance while reducing processing time.
3Reliability
If a larger permutation network is implemented, then decoding performance is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes redundant permutation layers that consume power without contributing to decoding performance. This extraction reduces the total number of active components, thereby lowering power consumption while preserving essential decoding functionality.
Solution Approach 2:
The patent segments the permutation network to identify and retain only the functional layers necessary for decoding performance. This segmentation reduces the overall power consumption by eliminating unnecessary layers while maintaining the performance of essential layers.
4Reliability
If a larger permutation network is used, then decoding capability is improved, but heat generation increases
Solution Approach 1:
The patent removes redundant permutation layers that generate heat without contributing to decoding capability. By extracting these unnecessary layers, the system reduces the total heat generation while maintaining the decoding capability provided by the essential layers.
Solution Approach 2:
The patent segments the permutation network to separate functional layers from redundant layers. This segmentation allows the system to retain only the layers necessary for decoding capability, thereby reducing heat generation from unnecessary components.
5Adaptability or versatility
If a full sized permutation network is implemented, then routing flexibility is improved, but routing complexity increases
Solution Approach 1:
The patent extracts and removes redundant routing paths and permutation layers that increase routing complexity without providing additional flexibility. The remaining essential layers maintain sufficient routing flexibility for decoding operations while reducing overall complexity.
Solution Approach 2:
The patent segments the routing structure into essential and redundant components, retaining only the necessary routing paths for decoding functionality. This segmentation reduces routing complexity while preserving the adaptability needed for effective decoding.
Data Source
AI summary
A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.