QC-LDPC Permutation Circuit Using Reduced Selector Networks

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Solution Overview

Problem

Conventional permutation networks for QC-LDPC decoders in rewritable non-volatile memory modules face challenges in reducing decoding time, power consumption, and hardware cost due to increased complexity and longer operation paths as the network size grows, making it difficult to efficiently correct errors in stored data.

Innovation Solution

A permutation network designing method that determines the optimal number of selectors and routing wires by calculating a second value based on a default dimension value and a saving parameter, constructing a permutation circuit with fewer layers and nodes, and strategically connecting them to reduce hardware cost and power consumption while maintaining decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full sized multilayer permutation network is implemented, then the decoding capability is improved, but the hardware cost and complexity increase due to more selectors and routing wires

Engineering Contradiction:

Improvedecoding capabilityVSAvoidhardware cost

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes redundant permutation layers from the full-sized multilayer permutation network. By analyzing the QC-LDPC code structure and identifying which permutation layers are actually necessary for error correction, the invention eliminates unnecessary layers, selectors, and routing wires, thereby reducing hardware cost while preserving essential decoding capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a simplified permutation network structure that uses fewer selectors and routing wires compared to the conventional full-sized network. This disposable-like approach accepts a reduced but sufficient permutation capability in exchange for significantly lower hardware cost, making the decoder more economical without sacrificing essential error correction function.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

2Reliability

If a full sized multilayer permutation network is implemented, then the decoding capability is improved, but the processing cycle becomes longer due to longer operation paths

Engineering Contradiction:

Improvedecoding capabilityVSAvoidprocessing cycle

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent removes redundant permutation layers that contribute to longer operation paths without providing essential decoding capability. By extracting only the necessary permutation operations needed for QC-LDPC error correction, the invention shortens the signal propagation path and reduces the processing cycle while maintaining adequate decoding performance.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent skips unnecessary permutation layers in the decoding process. By identifying and bypassing redundant permutation operations that do not contribute to error correction, the invention allows the decoding signal to pass through more directly, reducing the overall processing time and cycle duration.

Inventive Principle:

Principle #21Skipping (Rushing through)

3Reliability

If a full sized multilayer permutation network is implemented, then the decoding capability is improved, but the power consumption increases due to more selectors and routing wires

Engineering Contradiction:

Improvedecoding capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and eliminates redundant selectors and routing wires from the full-sized permutation network. Since each selector and routing wire consumes power, removing unnecessary components directly reduces the overall power consumption of the decoder while preserving the minimum required permutation capability for effective QC-LDPC decoding.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent adopts a simplified permutation network with fewer active components (selectors and routing wires) that consumes less power. This approach trades some permutation complexity for reduced power consumption, making the decoder more energy-efficient while maintaining sufficient error correction capability for practical applications.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS10700708B2Permutation network designing method, and permutation circuit of QC-LDPC decoder

Publication Date: 2020.06.30 SHENZHEN EPOSTAR ELECTRONICS LTD

AI summary

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.