QDE-Zipper FEC Code Reduces Decoding Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional spatially coupled product-like FEC schemes, such as staircase and zipper codes, experience high decoding memory and latency at ultra-low overheads, which is unacceptable for high-speed optical communication systems, and are prone to error floors due to stall patterns.
Innovation Solution
The introduction of a quasi-diagonal (QD) interleaver map and additional virtual buffers with distinct interleaver maps reduces decoding memory and latency, while providing sharp waterfall performance and additional bit protection levels, exemplified by the QDE-zipper code, which employs multiple virtual buffers and interleaver maps to enhance error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional spatially coupled product-like FEC schemes (staircase and zipper codes) are used with ultra-low overheads, then error correction performance approaches BSC channel capacity, but decoding memory size and latency become comparatively large and unacceptable
Solution Approach 1:
The patent segments the single large decoding buffer into multiple smaller buffers (first buffer, second buffer, third buffer) that process data in parallel stages. This segmentation reduces the memory size required at any single point while maintaining the overall error correction performance through coordinated processing across all buffer segments.
Solution Approach 2:
The patent implements dynamic buffer management where buffers are selectively activated and deactivated based on the processing stage. The first buffer processes initial data, then transitions to the second buffer, and finally to the third buffer, creating a dynamic flow that reduces peak memory requirements compared to static conventional approaches.
2Reliability
If conventional spatially coupled product-like FEC schemes are used with ultra-low overheads, then error correction performance approaches BSC channel capacity, but decoding memory size becomes comparatively large and unacceptable
Solution Approach 1:
The patent segments the decoding memory into multiple smaller buffers (first buffer, second buffer, third buffer) that operate in sequence. Each buffer holds only the portion of data needed for its specific processing stage, reducing the peak memory size compared to conventional schemes that require entire code blocks to be stored simultaneously.
Solution Approach 2:
The patent performs preliminary error correction processing in the first buffer before data is fully received and processed through all stages. This preliminary action allows earlier release of memory resources, reducing the total decoding memory size required while maintaining final error correction performance.
Data Source
AI summary
There is provided methods and processors for executing Forward Error Correction (FEC) coding. The method includes acquiring a stream of real data symbols from a communication medium. The stream of real data symbols being arranged in a real matrix. The method includes generating virtual data symbols being arranged in a virtual matrix. The generating includes applying an interleaver map onto the matrix such that (i) at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of (ii) real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1. The method includes decoding codewords formed by the virtual matrix and the matrix.