Quasi-Delay-Insensitive Interconnects for 3D Stacked Systems
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Solution Overview
Problem
3D-stacked systems face significant delay variations due to global variations across different wafers, leading to increased overheads in timing margins, power consumption, and reduced performance, especially in heterogeneous stacking scenarios where different technology process nodes are used.
Innovation Solution
A quasi-delay-insensitive (QDI) circuit design is implemented for point-to-point communication in 3D-stacked systems, utilizing hybrid bonding for high-density and high-performance interconnects, and is compatible with any system-on-chip protocol, allowing for robustness against delay variations without relying on through silicon via processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronous interconnect designs are used in 3D-stacked systems, then timing margins can be established, but delay variations due to global variations across different wafers increase overheads in timing margins and reduce performance
Solution Approach 1:
The patent replaces the traditional synchronous timing mechanism with an asynchronous handshake protocol. Instead of relying on clock-synchronized timing margins, the system uses request-acknowledge signal exchanges between transmitter and receiver modules. This substitution eliminates the need for conservative timing margins while maintaining reliable communication across dies with varying delay characteristics.
Solution Approach 2:
The invention changes the fundamental parameter from synchronous clock timing to asynchronous event-driven timing. By transitioning from fixed timing margins to dynamic handshake protocols, the system adapts to varying inter-die delay conditions without requiring predetermined safety margins, thereby improving performance while maintaining reliability.
2Reliability
If traditional synchronous interconnect designs are used in 3D-stacked systems, then timing control can be maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic handshake actions instead of continuous clocked operations. The asynchronous protocol activates communication only when data needs to be transferred, using periodic request-acknowledge cycles. This eliminates the continuous power consumption associated with clock distribution and timing control circuits in synchronous designs, reducing overall power usage while maintaining timing control through event-driven signaling.
3Quantity of substance
If hybrid bonding is used for interconnects, then high-density interconnects are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnect structure into discrete hybrid bonding interfaces between adjacent dies. Each interface is independently formed with controlled density, allowing the complex high-density bonding to be achieved in localized regions rather than across entire wafer surfaces. This segmentation enables manageable manufacturing processes while achieving overall high interconnect density in the 3D-stacked system.
Data Source
AI summary
A device for reducing the effects of variation in inter-die communication in 3D-stacked systems may include a die-to-die interconnect that includes a first module configured to convert data from a first synchronous domain to a dual-rail quasi-delay-insensitive format and a second module configured to convert the data from the dual-rail quasi-delay-insensitive format to a second synchronous domain. Various other devices, systems, and methods of manufacture are also disclosed.