QDR Controller Clock Phase Calibration for Read Delay Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing QDR controllers face challenges with long read delay times and dependence on programmable delay elements, limiting their efficiency and implementation flexibility.
Innovation Solution
A QDR controller design incorporating an arbiter, control state machine, read data sampling clock generating module, and read data path calibrating module, which generates sampling clocks with the same source and frequency but different phases to synchronize read data from non-system clock domains to the system clock domain, eliminating the need for programmable delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFO is used to synchronize read data to the system clock domain, then reliability is improved, but reading delay becomes long (generally longer than 8 clock cycles)
Solution Approach 1:
The patent replaces the traditional asynchronous FIFO mechanism (mechanical/system-level component) with a clock phase adjustment mechanism. By generating multiple phase-shifted sampling clocks (0°, 90°, 180°, 270°) and selecting the appropriate phase to capture read data, the system achieves synchronization with much shorter delay (6-8 clock cycles) while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of sampling clock phase to optimize the synchronization process. By adjusting the phase of sampling clocks and selecting the best phase match between read data and system clock, the system reduces reading delay while ensuring reliable synchronization without requiring long FIFO buffers.
2Loss of time
If a programmable delay element is used to synchronize read data, then reading delay is reduced (6-8 clock cycles), but implementation becomes impossible in ASIC factories that do not configure programmable delay elements
Solution Approach 1:
The patent creates a universal synchronization mechanism that works across different ASIC fabrication environments. By using fixed-phase clock generation (0°, 90°, 180°, 270°) and phase selection logic that does not require programmable delay elements, the design achieves portability and implementability in any standard ASIC factory while maintaining short reading delay.
Solution Approach 2:
The patent replaces expensive and less available programmable delay elements with simpler, more universally available fixed-phase clock generation circuits. The phase selection logic uses basic combinational logic and flip-flops that are standard in all ASIC processes, making the design more accessible and cost-effective.
3Loss of time
If multiple sampling clocks with different phases are generated and used for data path calibration, then reading delay is reduced and programmable delay elements are eliminated, but device complexity increases
Solution Approach 1:
The patent segments the sampling process into multiple fixed-phase clock signals (0°, 90°, 180°, 270°), each handling specific data capture scenarios. This segmentation allows the system to address different timing conditions with dedicated clock phases, reducing the need for complex programmable delay logic while achieving short reading delay.
Solution Approach 2:
The patent performs preliminary calibration to determine the optimal phase relationship between read data and system clock before normal operation. By pre-establishing the phase mapping through calibration sequences and storing the results in lookup tables, the system eliminates the need for complex real-time delay adjustment during data access, reducing both reading delay and operational complexity.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in "read data path calibrating state"; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.