QED-H SoC Verification for Hardware Anomaly Detection
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Solution Overview
Problem
Traditional pre-silicon verification techniques are inadequate for contemporary systems-on-a-chip, being too slow and failing to effectively address electrical bugs, and existing Quick Error Detection (QED) methods do not work for non-software programmable hardware components like high-definition video accelerators and power management circuitry.
Innovation Solution
The Quick Error Detection - Hardware (QED-H) method generates high-level descriptions of digital hardware systems, embeds QED transformations, and compares software and hardware signatures to quickly detect and fix anomalies in SoC hardware components, including those not software programmable, with low error detection latency and minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional pre-silicon verification techniques are used, then verification can be performed, but the process is too slow and fails to effectively address electrical bugs
Solution Approach 1:
The verification process is segmented into multiple passes where the same hardware component is executed multiple times with different inputs or conditions. Each pass generates signatures that are compared to detect errors, allowing thorough verification without requiring sequential execution of all possible test cases, thus improving both reliability and productivity
Solution Approach 2:
QED transformations are embedded into the high-level description before generation, preparing error detection mechanisms in advance. The system performs preliminary signature generation and comparison setup, enabling rapid error detection during actual verification without requiring slow sequential testing
2Adaptability or versatility
If existing Quick Error Detection (QED) methods are used, then error detection can be achieved, but they do not work for non-software programmable hardware components
Solution Approach 1:
The QED-H method is designed to be universally applicable to all hardware components regardless of whether they are software-programmable or not. The same high-level description embedding and signature comparison mechanism works for diverse hardware components including video accelerators and power management circuitry, achieving both versatility and reliable error detection
Solution Approach 2:
The method creates a software emulation copy of the hardware component that mirrors its behavior. This software copy can be executed and analyzed independently, allowing QED transformations to be applied to non-programmable hardware by creating a programmable representation that produces identical signatures, thus extending adaptability while maintaining detection reliability
3Reliability
If comprehensive verification is performed to detect all errors, then reliability improves, but verification time increases significantly
Solution Approach 1:
The verification process uses periodic execution of the hardware component multiple times with different inputs or conditions. Instead of sequential exhaustive testing, the system performs periodic passes where signatures are generated and compared at each iteration, enabling comprehensive error detection through repeated sampling without the time cost of complete sequential verification
Solution Approach 2:
The system continuously compares hardware signatures with software signatures and uses this feedback to identify errors. When mismatches are detected, the system can immediately identify and report errors without continuing through all possible test cases, thus achieving comprehensive verification while reducing time by using feedback-driven early termination
Data Source
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AI summary
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods - which we call Quick Error Detection - Hardware (QED-H) - advantageously quickly detect and fix anomalies (bugs) within SoC hardware components - and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.