QED Command Shifter Injection for Memory Timing Delay Control
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Solution Overview
Problem
As the frequency range of semiconductor memory devices increases, the complexity and cost of the QED shifter's exit selection circuitry grow, leading to delays and inefficiencies in shifting commands, particularly due to varying path delays and CAS latency, which can result in impractically large and costly circuitry.
Innovation Solution
The QED shifter injects commands at a location based on CAS latency minus path delay, using a demultiplexer to shift delays to a less time-critical portion of the memory device, and operates in a half-frequency mode with two pipelines for even and odd clock assertions, allowing for single clock cycle shifts and swaps between pipelines to manage latency and reduce circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency range of the memory device is increased, then the operating speed and data rate are improved, but the complexity and size of the exit selection circuitry grows rapidly
Solution Approach 1:
The patent divides the QED shifter into multiple independent stages (first stage, second stage, third stage) with separate control logic for each stage. This segmentation allows each stage to be controlled independently based on frequency ranges, preventing the need for a single large complex exit selection circuitry that would grow with the total frequency range.
Solution Approach 2:
The patent implements dynamic control where the duration of shifting for each stage is adjustable based on the operating frequency range. The controller dynamically selects appropriate duration values from multiple options for each stage, allowing the system to adapt to different frequencies without requiring a fixed large circuitry design.
2Productivity
If the frequency range is increased, then the data rate is improved, but the range of different possible durations in the QED shifter increases, requiring larger adjustment circuits
Solution Approach 1:
The patent segments the duration adjustment into multiple stages, where each stage has its own duration control circuit. Instead of one large circuit handling the entire frequency range, each stage has a smaller circuit that handles a portion of the frequency range, reducing the complexity of individual adjustment circuits.
Solution Approach 2:
The patent applies partial action by dividing the total duration adjustment into partial adjustments across multiple stages. Each stage performs a partial shifting operation with its own duration control, and the combined effect achieves the total required duration adjustment without requiring any single circuit to handle the full range.
3Adaptability or versatility
If the QED shifter uses multiple stages with separate control, then the flexibility to handle varying path delays and CAS latency is improved, but the overall circuit complexity increases
Solution Approach 1:
The patent segments the QED shifter into multiple stages with separate control logic, where each stage can be independently configured to handle specific portions of the path delay and CAS latency variations. This segmentation provides flexibility while keeping individual stage circuits relatively simple.
Solution Approach 2:
The controller unit serves multiple functions by managing duration control for multiple stages, selecting appropriate duration values based on frequency range and operational requirements. This multi-functionality reduces the need for separate dedicated control circuits for each stage, thereby reducing overall circuit complexity while maintaining adaptability.
Data Source
AI summary
A memory device includes a command interface configured to receive a command from a host device. The memory device also includes a command shifter configured to receive the command. The command shifter includes a plurality of stages coupled in series and configured to delay the command. The command shifter comprises selection circuitry configured to receive the command and to select an insertion stage of the plurality of stages for the command. The selection circuitry is configured to select the insertion stage as a location to insert the command. The selected insertion stage is selected to control a duration of delay in the command shifter. The selection of the insertion stage is based at least in part on a path delay between a clock and a data pin of the memory device.