QFN Package Encapsulant Frame for Short-Isolated Lead Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional QFN devices face challenges in ensuring adequate separation between solder attaching peripheral landing regions and the die pad to prevent electrical shorts, while also dealing with the increased cost and manufacturing variability introduced by partially thinned lead-frames.
Innovation Solution
The proposed solution involves a QFN packaged semiconductor device design where the encapsulant material forms a frame extending below the lead-frame lower surface, eliminating the need for a partial thickness region in the lead-frame. This design ensures all bond sites are on full-thickness lead-frame, improving wire bonding reliability and simplifying the lead-frame structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the peripheral landing regions are recessed by partial thickness reduction of the lead-frame, then the separation between solder attaching peripheral landing regions and die pad is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent resolves the electrical short risk by transitioning from a two-dimensional planar separation approach to a three-dimensional solution. The encapsulant material is configured to extend below the lead-frame lower surface, creating a vertical separation dimension that prevents solder bridging between peripheral landing regions and the die pad without requiring complex lead-frame thinning structures.
Solution Approach 2:
The encapsulant material serves as an intermediary element that provides both mechanical support and electrical isolation. By configuring the encapsulant to extend beneath the lead-frame, it acts as a mediator that separates the peripheral landing regions from the die pad, eliminating the need for the lead-frame itself to provide complex separation structures.
2Object-affected harmful factors
If the lead-frame is partially thinned by etching or pressing, then the separation between landing regions is improved, but the manufacturing cost and variability increase
Solution Approach 1:
Instead of modifying the lead-frame in the horizontal plane through etching or pressing, the patent utilizes the vertical dimension by configuring the encapsulant material to extend below the lead-frame lower surface. This approach simplifies lead-frame manufacturing while achieving the necessary separation to prevent electrical shorts.
Solution Approach 2:
The encapsulant material is repurposed as an active separation element rather than merely a protective coating. By extending the encapsulant beneath the lead-frame, it becomes an intermediary structure that provides electrical isolation and mechanical support, eliminating the need for costly and variable lead-frame thinning processes.
3Length of moving object
If the peripheral landing regions approach close to the die, then the wire bond length is reduced, but the risk of electrical short increases
Solution Approach 1:
The patent allows peripheral landing regions to be positioned close to the die in the horizontal plane, reducing wire bond length, while preventing electrical shorts by utilizing the vertical dimension. The encapsulant material extends below the lead-frame to provide separation, enabling close horizontal spacing without compromising electrical isolation.
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
Disclosed is a QFN packaged semiconductor device (100), having a first major surface (102), an opposing second major surface (204) and sidewalls (206) therebetween, and comprising: a lead-frame (210), having a lead-frame lower surface and comprising a central die-pad region (212) and a plurality of peripheral landing regions (214); a semiconductor die (220), attached to the die-pad on a top surface thereof; a plurality of bond-wires (230) providing electrical connection between the semiconductor die (220) and the plurality of peripheral landing regions (214); and encapsulant material (240), encapsulating the semiconductor die (220) and bond-wires (230); wherein the encapsulant material (240) forms a frame (242) extending below the lead-frame lower surface, and defining the second major surface (204), the frame (242) having an opening therein in a central region thereof under the semiconductor die (220), and wherein the sidewalls (206) are spaced apart from the frame (242) thereby exposing the lead-frame lower surface at the plurality of peripheral landing regions.