QFN Lead Plating for Solder Wettability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with QFN packaging have low mounting strength and reliability on substrates due to the absence of plating layers on the end surfaces of leads, which affects solder wettability and connection reliability.
Innovation Solution
The semiconductor device features lead plating layers and die pad plating layers made of materials like Pd to improve solder wettability on both lower surfaces and outer end surfaces of leads, with a specific resin structure and manufacturing process that includes forming grooves and applying plating layers to expose these surfaces for better bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plating layers are formed only on lower surfaces of leads (conventional method), then manufacturing process is simple, but solder wettability and mounting reliability are poor
Solution Approach 1:
The patent applies preliminary action by forming plating layers on the outer end surfaces of leads before the dicing cutting process. This ensures that the plating surfaces are prepared in advance and protected during subsequent manufacturing steps, allowing solder to wet these surfaces effectively during mounting while avoiding the complexity of post-dicing plating operations.
Solution Approach 2:
The patent applies local quality by selectively forming plating layers only on specific surfaces that require improved solder wettability - namely the lower surfaces and outer end surfaces of leads. This targeted approach improves mounting reliability at critical locations without unnecessarily complicating the entire manufacturing process.
2Reliability
If plating layers are formed on outer end surfaces of leads, then solder wettability improves, but manufacturing process complexity increases
Solution Approach 1:
The plating operation is performed before dicing, preparing the outer end surfaces in advance. This preliminary plating simplifies the overall manufacturing flow by combining plating with other pre-dicing operations, and the plating layers are subsequently protected during handling and mounting processes.
Solution Approach 2:
The patent merges the plating operation with the pre-dicing manufacturing stage, combining multiple operations (lead preparation, plating, and sealing) into an integrated process flow. This reduces the total number of separate manufacturing steps and simplifies production while achieving improved connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and strength of the connection between the semiconductor device and the mounting substrate by ensuring that both lower and outer end surfaces of the leads are wetted by solder, improving the overall mounting process.
Implementation Method 1
lead plating layers arranged to improve solder wettability are formed on the lower surfaces and the outer end surfaces of the leads
Data Source
AI summary
A semiconductor device 1 includes a semiconductor chip 2, a plurality of leads 4, disposed in a periphery of the semiconductor chip 2, and a sealing resin 5, sealing the semiconductor chip 2 and the leads 4 such that lower surfaces 18 and outer end surfaces 20 at sides opposite the semiconductor chip 2 of the leads 4 are exposed. Lead plating layers 21 arranged to improve solder wettability are formed on the lower surfaces 18 and the outer end surfaces 20 of the leads 4.