QFN Leadframe Electroplating for Thick Tin Sidewall Contacts
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Solution Overview
Problem
Conventional Quad Flat No-leads (QFN) packages with pre-plated contacts on the bottom side face issues with solderability due to oxidized metal, nickel migration, and discoloration, which affect bondability and solder joint reliability, and existing electroless plating methods fail to achieve the desired tin thickness for automotive standards.
Innovation Solution
A method involving leadframe etching with a mask to form contact bars, followed by electroplating to achieve a thick tin layer on both the bottom and flanks of the leads, and subsequent removal of sacrificial tie bars during singulation, allowing for increased solderable area and improved solder joint reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electroless plating is used to plate contacts, then the plating process is simple, but the tin thickness is only 1.5-2.0 μm which is insufficient for automotive standards
Solution Approach 1:
The patent changes the plating method from electroless to electroplating, and adjusts plating parameters (current density, plating time, electrolyte composition) to achieve the required tin thickness of more than 5 μm while maintaining processability
Solution Approach 2:
The patent applies preliminary surface treatment (mechanical polishing, chemical etching, or plasma treatment) to the contact flanks before electroplating to ensure proper adhesion and uniform thickness distribution, which is critical for achieving the required plating quality
2Reliability
If contact width is increased to increase solder joint section, then solderability improves, but contact pitch decreases and migration risk increases
Solution Approach 1:
The patent transitions from two-dimensional bottom-side plating to three-dimensional flank plating, coating the vertical surfaces of the contacts. This dimensional change increases the effective solderable area without increasing the horizontal contact width, thereby maintaining adequate contact pitch and creepage distance while improving solder joint reliability
3Ease of manufacture
If pre-plating is applied to bottom side only, then leadframe cost is reduced, but solderability is compromised due to oxidized metal and nickel migration
Solution Approach 1:
The patent applies preliminary protective coating to the contact flanks before they are exposed to atmosphere, preventing oxidation and nickel migration. This preliminary protection ensures long-term solderability while maintaining cost-effectiveness
Solution Approach 2:
The patent employs inert or controlled atmosphere storage and handling procedures for the leadframe after plating but before final assembly, preventing atmospheric exposure that would cause oxidation and migration of nickel layers
4Area of stationary object
If thick tin plating (>5 μm) is applied to flanks, then solderable area increases, but plating process complexity increases
Solution Approach 1:
The patent applies plating selectively to specific regions (contact flanks) with different requirements. By controlling the plating process to deposit thicker tin only on the flank surfaces where solderability is critical, while maintaining thinner or no plating on other areas, the process achieves the required solderable area without unnecessary complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances solder joint reliability by increasing the solderable area, achieving a thicker tin layer than conventional methods, and simplifies leadframe design and processing, reducing costs while maintaining a high number of I/O pins and minimizing creepage distance issues.
Implementation Method 1
facilitate plating contact pads, including the flanks, with a tin layer having a thickness of more than 5 microns, via an electroplating process, for instance
Data Source
AI summary
A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.