Low-profile QFN Package with Segmented Dielectric and Encapsulation Layers
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Solution Overview
Problem
The challenge is to create low-profile electronic packages for semiconductor devices that can accommodate wirebonded components within increasingly compact enclosures without compromising performance or reliability, particularly for applications like fingerprint scanners that require precise dielectric material control.
Innovation Solution
The solution involves a quad-flat no lead (QFN) architecture where a semiconductor die is disposed within a leadframe opening, with a dielectric material encapsulating the die and a thin encapsulation layer formed over the active surface, allowing for a thickness ratio of the die to leadframe where the die is at least 50% thicker, and wirebonds with a maximum height of 50 microns, enabling a compact and reliable package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the electronic package is made compact to fit shrinking enclosures, then the profile height is reduced, but the dielectric material thickness control becomes more difficult
Solution Approach 1:
The encapsulation structure is divided into two distinct segments: a dielectric material layer and a separate encapsulation layer. This segmentation allows independent control of each layer's thickness and properties, enabling precise dielectric material thickness control even in low-profile packages where the total height is reduced.
Solution Approach 2:
Different material layers are assigned specific local functions: the dielectric material layer provides electrical isolation and mechanical support directly over the die, while the encapsulation layer provides environmental protection. This local quality differentiation allows the dielectric layer to be precisely controlled for thickness while the overall package maintains a low profile.
2Length of moving object
If the die thickness is increased to at least 50% of leadframe thickness for low-profile design, then the package becomes more compact, but the wirebond height clearance becomes more constrained
Solution Approach 1:
The design transitions from vertical wirebond clearance management to a planar configuration where wirebonds are contained within the encapsulation layer's horizontal space. By reducing the die thickness to 50% or less of the leadframe thickness and containing wirebonds within the encapsulation layer, the design utilizes the planar dimensions of the leadframe opening rather than requiring vertical clearance.
3Manufacturing precision
If a thin encapsulation layer is formed over the die for fingerprint scanner applications, then the dielectric control is improved, but the moisture protection capability is reduced
Solution Approach 1:
The protective structure is segmented into functional layers: the dielectric material layer provides precise thickness control for fingerprint scanner performance, while a separate encapsulation layer provides moisture and environmental protection. This segmentation allows the thin dielectric layer (100 microns or less) to maintain precision without compromising reliability, as the encapsulation layer assumes the protection function.
Data Source
AI summary
An electronic package is formed by placing a semiconductor die within an opening in a leadframe and performing a first molding operation. The die is wirebonded to the leadframe and a final encapsulation is performed with a second molding operation.