QFN Package Enhancement Elements for Solder Joint Reliability

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Solution Overview

Problem

Conventional quad-flat no-leads (QFN) semiconductor device packages experience weak solder joint reliability at the corners, which is a critical issue during drop tests, as the solder joints tend to break at these points, necessitating an enhancement to improve connection strength.

Innovation Solution

The introduction of enhancement elements with larger surface areas around the die pad and leads, which are partially exposed and connected via solder joints, increases the contact area and strength, enhancing the solder joint reliability between the semiconductor device package and the PCB.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional QFN package structure is used, then device complexity is reduced and manufacturing is simplified, but solder joint strength at corners deteriorates and reliability decreases

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The package structure is segmented into conventional leads and additional enhancement elements. The enhancement elements are separate structural components attached to the package body, allowing the core QFN structure to remain simple while adding localized reinforcement at corner positions where solder joints are weakest.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Enhancement elements are strategically placed at specific locations (corners and edges) of the package where solder joint strength is most critical. This localized approach reinforces only the weak points rather than uniformly increasing complexity across the entire package structure.

Inventive Principle:
Principle #3Local quality

2Strength

If enhancement elements with larger surface area are added, then solder joint strength is improved, but device complexity increases

Engineering Contradiction:
Improvesolder joint strengthVSAvoidnumber of components
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The enhancement elements are designed to be integrated with the lead frame structure during the molding process. Multiple enhancement elements are combined into a single molded component that forms part of the package body, reducing the number of separate parts while maintaining the strength benefits of increased solder contact area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The enhancement elements serve multiple functions: they increase solder joint strength through larger contact area, provide structural reinforcement at critical positions, and maintain compatibility with standard QFN packaging processes. This multi-functionality justifies the added complexity by delivering multiple benefits from a single design feature.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If enhancement elements are partially exposed, then solder contact area is increased, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesolder contact areaVSAvoidexposure alignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The enhancement elements are pre-formed with defined exposure surfaces before the molding process. The molding compound is then applied to expose specific portions of these pre-formed elements, allowing precise control over the exposed areas. This preliminary formation of enhancement elements simplifies the subsequent molding process and reduces precision requirements during assembly.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8994156B2Semiconductor device packages with solder joint enhancement elements
Publication Date: 2015.03.31 ADVANCED SEMICON ENG INC
  • US8994156B2 patent drawing
  • US8994156B2 patent drawing
  • US8994156B2 patent drawing

AI summary

Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.