Dynamic Start Voltage Programming for QLC Memory Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory sub-systems using quad-level cell (QLC) memory devices face performance issues due to the lengthy programming time caused by intermediate program verify operations, which add latency and impact the quality of service.
Innovation Solution
Implementing all levels dynamic start voltage (DSV) programming, where multiple programming levels are applied before a single program verify operation, reducing the number of transitions between programming phases and verify phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If intermediate program verify operations are performed after each programming level, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent applies preliminary action by performing all programming operations before any verify operation. Multiple programming pulses are applied sequentially to reach all target programming levels, and only after completing all programming does the system perform the verify operation. This eliminates the need for intermediate verify operations that would interrupt the programming process, thereby reducing total programming time while maintaining precision through the comprehensive final verify.
2Manufacturing precision
If multiple programming levels are programmed sequentially with intermediate verify operations, then data storage accuracy is improved, but quality of service deteriorates
Solution Approach 1:
The patent merges multiple programming operations and the verify operation into a single continuous process. Instead of alternating between programming and verifying at each level, the system combines all programming pulses for different levels into one uninterrupted sequence, followed by a single comprehensive verify operation. This merging eliminates repeated transitions between programming and verify phases, reducing latency and improving quality of service while maintaining data storage accuracy through thorough programming and comprehensive verification.
3Reliability
If intermediate program verify operations are performed, then programming reliability is improved, but programming speed decreases
Solution Approach 1:
The patent implements continuity of useful action by maintaining a continuous programming sequence without interruption for verify operations. The system applies programming pulses for all levels sequentially in one continuous phase, then performs the verify operation once at the end. This continuous approach eliminates the stop-start nature of intermediate verify operations, maintaining programming reliability through comprehensive verification while significantly improving programming speed by eliminating delays from frequent verify interruptions.
Data Source
AI summary
Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.