QLC Memory Encoding with Gray-Constrained Mapping for Read Accuracy

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Solution Overview

Problem

Quadruple-level cell (QLC) memory devices face inter-cell interference issues due to encoding schemes that lead to errors in data read operations, particularly when cells in low program-voltage levels are surrounded by cells in high program-voltage levels, causing read reference voltage levels to increase and result in incorrect data retrieval.

Innovation Solution

A jointly designed Gray coding and constrained coding scheme is implemented to map program-voltage levels into four logical pages, balancing the number and quality of sensing operations required for read operations, with Gray mapping allowing identification of harmful inter-cell interference patterns using only two logical pages and minimizing random read performance degradation by avoiding certain interference patterns through constrained coding across two logical pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional encoding schemes are used for QLC memory devices, then data storage capacity is achieved, but inter-cell interference causes errors in data read operations

Engineering Contradiction:
Improvedata read accuracyVSAvoidinter-cell interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the encoding parameters by using a jointly designed Gray coding and constrained coding scheme. The Gray code mapping is optimized to minimize bit transitions between adjacent program-voltage levels, and the constrained code limits the number of consecutive cells at extreme voltage levels. This parameter optimization reduces inter-cell interference and improves read accuracy without sacrificing storage capacity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent combines two different coding schemes (Gray coding and constrained coding) into a composite encoding system. The Gray code provides efficient voltage-level-to-bit mapping, while the constrained code adds protective constraints against interference. This composite approach leverages the strengths of both coding methods to simultaneously achieve high storage efficiency and robust interference resistance.

Inventive Principle:
Principle #40Composite materials

2Ease of operation

If Gray code mapping is used to map program-voltage levels into logical pages, then sensing operations are simplified, but harmful inter-cell interference patterns still occur

Engineering Contradiction:
Improvesensing operation complexityVSAvoidinter-cell interference patterns
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent modifies the Gray code mapping parameters by jointly designing the code assignment to avoid harmful patterns. Specifically, the code assignment is optimized so that cells at extreme program-voltage levels (which cause maximum interference) are not positioned in configurations that create harmful interference patterns. This parameter optimization maintains the simplicity of sensing operations while eliminating the harmful effects.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If constrained coding is applied across logical pages to prevent interference patterns, then read reliability improves, but encoding complexity increases

Engineering Contradiction:
Improveread reliabilityVSAvoidencoding scheme complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines Gray coding and constrained coding into a unified composite encoding scheme. The Gray code component handles the basic voltage-to-bit mapping efficiently, while the constrained code component adds targeted protection against interference. This composite structure achieves high read reliability without requiring a completely complex re design of the entire encoding system, as each component builds on the previous one.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10846172B2Encoding method and system for memory device including QLC cells
Publication Date: 2020.11.24 SK HYNIX INC
  • US10846172B2 patent drawing
  • US10846172B2 patent drawing
  • US10846172B2 patent drawing

AI summary

Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a first encoder and a second encoder. The first encoder encodes, based on a constrained code, a first group of data to generate a third group of data, the first group of data corresponding to first and third logical pages among a plurality of logical pages. The second encoder encodes, based on a Gray code, a second group of data and the third group of data to generate encoded sequences corresponding to a plurality of program-voltage (PV) levels, the second group of data corresponding to the second and fourth logical pages among the plurality of logical pages.